cs4365 Cirrus Logic, Inc., cs4365 Datasheet - Page 44
cs4365
Manufacturer Part Number
cs4365
Description
114 Db, 192 Khz 6-channel D/a Converter
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS4365.pdf
(52 pages)
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44
6.12
6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV)
Reserved
0
7
PCM Clock Mode (address 16h)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
Reserved
6
0
MCLKDIV
5
0
Reserved
0
4
Reserved
3
0
Reserved
2
0
Reserved
0
1
Reserved
CS4365
DS670F2
0
0
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