ad5501 Analog Devices, Inc., ad5501 Datasheet - Page 11

• Manufacturer Part Number: ad5501
• Description: High Voltage, 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
THEORY OF OPERATION
The AD5501 contains a 12-bit DAC, an output amplifier and a
precision reference in a single package. The architecture of the
DAC channel consists of a 12-bit resistor-string DAC followed
by an output buffer amplifier. The part operates from a single
supply voltage of 10V to 62V. The DAC output voltage range is
selected via the range-select, R_SEL , pin. The DAC output
range is 0V to 30 V if R_SEL is held high and 0V to 60 V if
R_SEL is held low. Data is written to the AD5501 in a 16-bit
word format (see Table 7), via a serial interface.
POWER-UP STATE
On power-up, the Power-on-Reset circuitry clears the bits of the
Control register (see Table 9) to 0. This ensures that the analog
section is initially powered down, which helps reduce power
consumption, and that the thermal shutdown mode is enabled
but not activated. This allows the user to program the DAC
register to the required value while typically consuming only
TBD
ensures that the input and DAC registers power up in a known
condition, 0x000, and remain there until a valid write to the
device has taken place. The analog section can be powered up
by setting bit C2 of the Control register to 1.
POWER-DOWN MODE
The DAC channel can be powered up or powered down by
programming bit C2 in the Control register (see Table 9). When
the DAC channel is powered down the associated analog
circuitry is turn off to reduce power consumption. The digital
section of the AD5501 remains powered up. The output of the
DAC amplifier can be three-stated or connected to AGND via
an internal 20kΩ resistor depending on the state of bit C6 in the
Control register. The power-down mode does not change the
contents of the DAC register. This ensures that the DAC
channel returns to its previous voltage when the power-down
bit is set to 1. The AD5501 also offers the user the flexibility of
updating the DAC registers during power-down. The Control
register can be read back at any time to check the status of the
bits.
DAC CHANNEL ARCHITECTURE
The architecture of the DAC channel consists of a 12-bit
resistor-string DAC followed by an output buffer amplifier (see
Figure 11). The resistor-string section is simply a string of
resistors, each of value R, from V
reference, to AGND. This type of architecture guarantees DAC
monotonicity. The 12-bit binary digital code loaded to the DAC
register determines at which node on the string the voltage is
tapped off before being fed into the output amplifier. The data
format for the AD5501 is straight binary as shown in Table 6.
The output amplifier multiplies the DAC output voltage to give
a fixed linear voltage output range of 0 to 60 V if R_SEL =0 or 0
to 30 V if R_SEL =1. Each output amplifier is capable of driving
a 40K
AGND +TBDV and V
μ
Ω
A of supply current. The power-on-reset circuitry also
load while allowing an output swing within the range of
DD
– TBDV.
REF
, generated by the precision
Rev. Pr B | Page 11 of 15
As the DAC architecture gives a fixed voltage output range of 0V
to 30 V or 0V to 60 V the user should set V
or 60.5 V to use the maximum DAC resolution.
Table 6. DAC Data Format
DAC Value
0b0000 0000 0000
0b0000 0000 0001
0b0000 0000 0010
0b0111 1111 1111
0b1000 0000 0000
0b1111 1111 1110
0b1111 1111 1111
V
The voltage feedback pin (V
the gain amplifier. It should be connected to the V
force-sense configuration, as shown in Figure 12, to compensate
for any voltage drop between the V
resistance between the VOUT and V
100Ω.
SELECTING THE OUTPUT RANGE
The output range of the DAC is selected by the R_SEL pin.
When the R_SEL pin is connected to logic 1 the DAC output
voltage can be set between 0V and 30 V. When the R_SEL pin is
connected to logic 0 the DAC output voltage can be set between
0V and 60 V. The state of R_SEL can be changed any time when
the serial interface is not being used, i.e. not during a read or
write operation. When the R_SEL pin is changed, the voltage on
the output pin remains the same until the next write to the DAC
register (and LDAC is brought low). For example, if the user
writes 0x800 to the DAC register when in 30 V mode ( R_SEL
REGISTER
FB
INPUT
PIN
12-BIT
DAC
Figure 12. V
12
128K
REGISTER
Figure 11. DAC Channel Architecture
DAC
FB
and V
OUTPUT
BUFFER
FB
OUT
30 V Mode
0.000000000
0.007324219
0.014648438
14.99267578
15.00000000
29.98535156
29.99267578
) is part of the feedback loop of
12
REFERENCE
force-sense configuration
PRECISION
2432K
AGND
DAC
OUT
FB
Output Voltage
pin and the load. The
pins should not exceed
V
V
OUT
FB
DD
GAIN
to at least 30.5 V
60 V Mode
0.000000000
0.014648438
0.029296875
29.98535156
30.00000000
59.97070313
59.98535156
OUT
AD5501
pin in a
R
V
L
OUT