ad5501 Analog Devices, Inc., ad5501 Datasheet - Page 13

• Manufacturer Part Number: ad5501
• Description: High Voltage, 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SERIAL INTERFACE
The AD5501 has a serial interface ( SYNC , SCLK, SDI and
SDO), which is compatible with SPI standards, as well as most
DSPs. The AD5501 allows writing of data, via the serial
interface, to the Input and Control registers. The DAC register
is not directly writeable or readable.
The input shift register is 16 bits wide (see Table 7). The 16-bit
word consists of one read/write (R/ W ) control bit, followed by
three address bits and twelve DAC data bits. Data is loaded MSB
first.
WRITE MODE
To write to a register the R/ W bit should be 0. The three address
bits then determine the register to update. The address bits (A2-
A0) should be 001 to write to the DAC Input register or 111 to
write to the Control register (see Table 8). Data is clocked into
the selected register during the remaining twelve clocks of the
same frame. Figure 3 shows a timing diagram of a typical
AD5501 write sequence. The write sequence begins by bringing
the SYNC line low. Data on the SDI line is clocked into the 16-
bit shift register on the falling edge of SCLK. On the 16th falling
clock edge, the last data bit is clocked in and the programmed
function is executed (that is, a change in the selected DAC Input
register or a change in the mode of operation). The AD5501
does not require a continuous SCLK and dynamic power can be
saved by only transmitting clock pulses during a serial write. At
this stage, the SYNC line can be kept low or be brought high. In
either case, it must be brought high for a minimum of 20 ns
before the next write sequence so that a falling edge of SYNC
can initiate the next write sequence. All interface pins should be
operated at close to the supply rails to minimize power
consumption in the digital input buffers.
Table 7. Input Register Format
DB15
R/ W
Table 8. Input Register Bit Functions
Bit
R/ W
A2,A1,A0
D11:D0
1
No Operation Command
DB14
A2
DB13
A1
Description
Indicates a read from or a write to the addressed register.
These bits determine if the Input register or the Control register is to be accessed.
A2
0
0
0
0
1
1
1
1
DB12
A0
DB11
DB10
A1
0
0
1
1
0
0
1
1
DB9
Rev. Pr B | Page 13 of 15
DB8
A0
0
1
0
1
0
1
0
1
DB7
READ MODE
The AD5501 allows data readback via the serial interface from
the DAC Input register and the Control register. In order to
read back a register, it is first necessary to tell the AD5501 that a
readback is required. This is achieved by setting the R/ W bit to
1. The three address bits then determine the register from
which data is to be read back. Data from the selected register is
clocked out of the SDO pin on the next twelve clocks of the
same frame.
The SDO pin is three-stated or connected to DGND via a 20kΩ
resistor (as determined by bit C6 of the Control register) but
becomes driven on the rising edge of the fifth clock pulse. The
pin remains driven until the registers data has been clocked out
or the SYNC pin is returned high. Figure 4 shows the timing
requirements during a read operation. Note that due to timing
requirements of t
interface during a read operation should not exceed 20MHz
Data Bits
DB6
Function/Address
NOP
DAC Input register
Reserved
Reserved
Reserved
Reserved
Reserved
Control register
Data
DB5
1
17
TBD(25ns) the maximum speed of the SPI
DB4
DB3
DB2
DB1
AD5501
DB0