ir3502b International Rectifier Corp., ir3502b Datasheet - Page 9

• Manufacturer Part Number: ir3502b
• Description: Xphase3 Control Ic
• Manufacturer: International Rectifier Corp.

SYSTEM THEORY OF OPERATION
System Description
The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The
control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three analog
buses, i.e., VDAC, EA, IIN. The digital buses are responsible for switching frequency determination and accurate
phase timing control without any external component. The analog buses are used for PWM control and current sharing
among interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK signals, error
amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by each phase of the
converter, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, Phase disable circuit, current
sensing and sharing, etc.
PWM Control Method
The PWM block diagram of the XPhase3
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the control IC is used for
the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM ramp
slope will change with the input voltage and automatically compensate for changes in the input voltage. The input
voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop
related to changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an
external resistor. The control IC system clock signal CLKOUT is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output PHSOUT is
Page 9 of 38
IVSETPT
VDRP
AMP
CONTROL IC
CLOCK GENERATOR
+
-
REMOTE SENSE
AMPLIFIER
+
-
IROSC
ERROR
AMPLIFIER
Compensation
Thermal
VDAC
VDAC
+
-
IIN
VN
VDAC_BUFF
VSETPT
IMON
VDRP
PHSOUT
PHSIN
VO
VDAC
LGND
EAOUT
FB
CLKOUT
RVSETPT
RTCMP3
CEA1
RTHERM
CEA
REA
RTCMP2
RTCMP1
RFB1
CFB1
TM
GATE DRIVE
VOLTAGE
RFB
RDRP
Figure 3 System Block Diagram
architecture is shown in Figure 3. Feed-forward voltage mode control with
PHSOUT
PHSOUT
PHSIN
CLKIN
ISHARE
DACIN
ISHARE
DACIN
EAIN
CLKIN
PHSIN
EAIN
3K
3K
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
Q
PWM
COMPARATOR
Q
PWM
COMPARATOR
+
-
+
-
RAMP
DISCHARGE
CLAMP
RAMP
DISCHARGE
CLAMP
ENABLE
ENABLE
1
-
1
VID6
-
VID6
+
VID6
VID6
+
VID6
VID6
-
+
-
+
+
-
+
-
PHASE IC
PHASE IC
2
2
PWM LATCH
BODY
BRAKING
COMPARATOR
PWM LATCH
BODY
BRAKING
COMPARATOR
DOMINANT
D
CLK
RESET
DOMINANT
D
CLK
RESET
VID6
VID6
VID6
DFFRH
VID6
Q
Q
U248
DFFRH
Q
Q
U246
+
+
+
+
CURRENT
SENSE
AMPLIFIER
CURRENT
SENSE
AMPLIFIER
OFF
OFF
OFF
VID6
OFF
VID6
VID6
+
-
VID6
+
-
PSI
CSIN-
CSIN-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
PSI
CSIN+
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
CCS
CCS
RCS
RCS
CBST
CBST
IR3502B
V3.2
COUT
PSI
PSI
VIN
VOSNS+
VOUT
GND
VOSNS-