ltc2222cuk-trpbf Linear Technology Corporation, ltc2222cuk-trpbf Datasheet

no-image

ltc2222cuk-trpbf

Manufacturer Part Number
ltc2222cuk-trpbf
Description
Ltc2223 - 12-bit, 80msps Adcs
Manufacturer
Linear Technology Corporation
Datasheet
FEATURES
APPLICATIO S
TYPICAL APPLICATIO
ANALOG
INPUT
REFH
REFL
Sample Rate: 105Msps/80Msps
68dB SNR up to 140MHz Input
80dB SFDR up to 170MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 475mW/366mW
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin QFN Package
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
+
CLOCK/DUTY
REFERENCE
INPUT
CONTROL
FLEXIBLE
ENCODE
S/H
CYCLE
INPUT
U
PIPELINED
ADC CORE
12-BIT
U
3.3V
V
DD
CORRECTION
LOGIC
DRIVERS
OUTPUT
DESCRIPTIO
The LTC
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2222/
LTC2223 are perfect for demanding communications
applications with AC performance that includes 68dB SNR
and 80dB spurious free dynamic range for signals
up to 170MHz. Ultralow jitter of 0.15ps
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
A separate output power supply allows the outputs to drive
0.5V to 3.6V logic.
The ENC
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
All other trademarks are the property of their respective owners.
22201 TA01
, LTC and LT are registered trademarks of Linear Technology Corporation.
®
+
2222 and LTC2223 are 105Msps/80Msps, sam-
D11
0V
0.5V TO 3.6V
0GND
D0
and ENC
DD
U
LTC2222/LTC2223
inputs may be driven differentially or
RMS
100
12-Bit,105Msps/
95
90
85
80
75
70
65
60
.
0
80Msps ADCs
SFDR vs Input Frequency
100
INPUT FREQUENCY (MHz)
200
4th OR HIGHER
300
2nd or 3rd
400
RMS
500
allows
22223 TA01b
22223fa
1
600

Related parts for ltc2222cuk-trpbf

ltc2222cuk-trpbf Summary of contents

Page 1

... PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners ...

Page 2

... ORDER PART NUMBER LTC2222CUK LTC2223CUK LTC2222IUK LTC2223IUK Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges ...

Page 3

ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are 25°C. (Note 4) A SYMBOL PARAMETER V Analog Input Range ( Analog ...

Page 4

LTC2222/LTC2223 TER AL REFERE CE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, ...

Page 5

W U POWER REQUIRE E TS range, otherwise specifications are at T SYMBOL PARAMETER V Analog Supply Voltage DD OV Output Supply Voltage DD IV Analog Supply Current DD P Power Dissipation DISS P Shutdown Power SHDN P Nap Mode ...

Page 6

LTC2222/LTC2223 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2222: INL, 2V Range 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 4096 OUTPUT CODE 2222 G01 LTC2222: SNR vs Input Frequency, –1dB, 1V Range ...

Page 7

W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2222: SFDR and SNR vs Sample Rate, 1V Range 30MHz, –1dB IN 100 95 90 SFDR SNR 100 ...

Page 8

LTC2222/LTC2223 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2222: 8192 Point FFT 70MHz, –1dB, 1V Range IN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 9

W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2223: INL, 2V Range 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 4096 OUTPUT CODE 2223 G01 LTC2223: SNR vs Input Frequency, –1dB, 1V Range 70 ...

Page 10

LTC2222/LTC2223 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2223: SFDR and SNR vs Sample Rate, 1V Range 30MHz, –1dB IN 100 95 90 SFDR SNR 100 ...

Page 11

W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2223: 8192 Point FFT 70MHz, –1dB, 1V Range IN 0 – 10 – 20 – 30 – 40 – 50 – 60 – 70 – 80 – 90 – 100 – ...

Page 12

LTC2222/LTC2223 CTIO (Pin 1): Positive Differential Analog Input – (Pin 2): Negative Differential Analog Input. IN REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins 5, 6 with 0.1µF ...

Page 13

U U FUNCTIONAL BLOCK DIAGRA + A IN INPUT FIRST PIPELINED S/H ADC STAGE – 1.6V REFERENCE 2.2µF RANGE SELECT REF SENSE BUF DIAGRA S ANALOG INPUT – ENC + ...

Page 14

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all ...

Page 15

U U APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2222/LTC2223 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five ...

Page 16

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from ...

Page 17

U U APPLICATIO S I FOR ATIO Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input ...

Page 18

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO HIGH SPEED DIFFERENTIAL AMPLIFIER 25Ω ANALOG + 3pF + INPUT CM – – 25Ω 3pF AMPLIFIER = LTC6600-20, LT1993, ETC. Figure 4. Differential Drive with an Amplifier 0.1µF 12Ω ANALOG INPUT 0.1µF ...

Page 19

U U APPLICATIO S I FOR ATIO 0.1µF 4.7nH ANALOG INPUT 0.1µF 25Ω T1 0.1µF 25Ω 4.7nH T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz 1.6V ...

Page 20

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise perfor- mance while maintaining excellent SFDR. The 1V input range will ...

Page 21

U U APPLICATIO S I FOR ATIO The lower limit of the LTC2222/LTC2223 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage ...

Page 22

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO Data Format The LTC2222/LTC2223 parallel digital output can be se- lected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3V ...

Page 23

U U APPLICATIO S I FOR ATIO to recharge and stabilize. Connecting SHDN GND results in nap mode, which typically dissipates 35mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap ...

Page 24

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO Clock Sources for Undersampling Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that ...

Page 25

U U APPLICATIO S I FOR ATIO R19 R1* C1 OPT 0.1µF T1* R2 ANALOG 24.9 INPUT J1 C2 0.1µF R6 0.1µ 1µF ...

Page 26

LTC2222/LTC2223 U U APPLICATIO S I FOR ATIO Layer 1 Component Side Layer 3 Power Plane Silkscreen Top Layer 2 GND Plane Layer 4 Bottom Side 22223fa ...

Page 27

... PIN 1 TOP MARK (SEE NOTE 5) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights Package 48-Lead Plastic QFN (7mm × ...

Page 28

... High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz 12.5dB, 500Ω Single-Ended RF and LO Ports www.linear.com ● 22223fa LT 0106 REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2004 ...

Related keywords