ltc2226iuh-trpbf Linear Technology Corporation, ltc2226iuh-trpbf Datasheet - Page 17

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ltc2226iuh-trpbf

Manufacturer Part Number
ltc2226iuh-trpbf
Description
Ltc2227 - 12-bit, 40msps Low Power 3v Adcs
Manufacturer
Linear Technology Corporation
Datasheet
APPLICATIO S I FOR ATIO
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
should be driven with the input signal and A
connected to 1.5V or V
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The V
31) may be used to provide the common mode bias level.
V
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2228/LTC2227/LTC2226
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
input reactance can influence SFDR. At the falling edge of
CLK, the sample-and-hold circuit will connect the 4pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when CLK rises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
CM
can be tied directly to the center tap of a transformer
U
CM
U
.
Figure 3. Single-Ended to Differential Conversion Using a Transformer
CM
pin must be bypassed to
ANALOG
W
INPUT
CM
output pin (Pin
0.1µF
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
IN
U
should be
1:1
T1
25Ω
25Ω
IN
+
0.1µF
25Ω
25Ω
1/(2F
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2228/LTC2227/LTC2226 being
driven by an RF transformer with a center tapped second-
ary. The secondary center tap is DC biased with V
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies be-
low 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
LTC2228/LTC2227/LTC2226
ENCODE
2.2µF
12pF
V
A
A
CM
IN
IN
+
); however, this is not always possible and the
LTC2228/27/26
222876 F03
17
222876fa
CM
,

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