ltc2258cuj-14 Linear Technology Corporation, ltc2258cuj-14 Datasheet - Page 16

• Manufacturer Part Number: ltc2258cuj-14
• Description: 14-bit, 65/40/25msps Ultralow Power 1.8v Adcs
• Manufacturer: Linear Technology Corporation

LTC2258-14
LTC2257-14/LTC2256-14
PIN FUNCTIONS
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1
21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
16
FUNCTIONAL BLOCK DIAGRAM
–
/D0_1
SENSE
0.1μF
1μF
V
A
A
V
REF
IN
IN
CM
+
–
+
to D12_13
INPUT
REFERENCE
S/H
SELECT
RANGE
1.25V
V
DD
/2
REF
BUF
–
/D12_13
FIRST PIPELINED
ADC STAGE
+
(Pins 17/18, 19/20,
AMP
DIFF
REF
SECOND PIPELINED
ADC STAGE
0.1μF
Figure 1. Functional Block Diagram
REFH
REFH
0.1μF
2.2μF
REFL
THIRD PIPELINED
REFL
ADC STAGE
0.1μF
INTERNAL CLOCK SIGNALS
CLOCK/DUTY
ENC
CONTROL
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT
CLKOUT
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT
CLKOUT
by programming the mode control registers.
OF
is high when an overfl ow or underfl ow has occurred.
CYCLE
+
–
ENC
/OF
–
FOURTH PIPELINED
ADC STAGE
+
+
+
–
(Pins 35/36): Over/Under Flow Digital Output. OF
PAR/SER
/CLKOUT
can also be delayed relative to the digital outputs
is high.
CS
REGISTERS
CONTROL
MODE
SCK
+
FIFTH PIPELINED
SDI
ADC STAGE
(Pins 27/28): Data Output Clock.
SDO
AND CORRECTION
SHIFT REGISTER
DRIVERS
OUTPUT
OGND
+
225814 F01
+
is low. The odd
. The phase of
•
•
•
OV
D0
GND
OF
D13
CLKOUT
CLKOUT
V
DD
DD
+
–
225814p
+