ltc2258cuj-14 Linear Technology Corporation, ltc2258cuj-14 Datasheet - Page 22

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ltc2258cuj-14

Manufacturer Part Number
ltc2258cuj-14
Description
14-bit, 65/40/25msps Ultralow Power 1.8v Adcs
Manufacturer
Linear Technology Corporation
Datasheet

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Part Number:
ltc2258cuj-14#PBF
Manufacturer:
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Quantity:
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LTC2258-14
LTC2257-14/LTC2256-14
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT
so the rising edge of CLKOUT
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT
setup-and-hold time when latching the data, the CLKOUT
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2258-14/LTC2257-14/LTC2256-14 can also phase
shift the CLKOUT
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
22
+
and CLKOUT
+
/CLKOUT
, independently of the phase shift.
D0-D13, OF
CLKOUT
ENC
signals by serially program-
+
+
+
can be used to latch the
+
. To allow adequate
Figure 14. Phase Shifting CLKOUT
+
+
,
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overfl ow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
A
(2V Range)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
≤–1.000000V
225814 F14
IN
PHASE
+
SHIFT
135°
180°
225°
270°
315°
45°
90°
– A
IN
CLKINV
0
0
0
0
1
1
1
1
OF
MODE CONTROL BITS
1
0
0
0
0
0
0
0
0
1
CLKPHASE1
(OFFSET BINARY)
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
D13-D0
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
(2’s COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
D13-D0
225814p

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