st52f510 STMicroelectronics, st52f510 Datasheet - Page 91

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

Figure 14.4 Event Flags and Interrupt Generation
Note: The I
the corresponding Enable Control Bit (ITE) is set and the Interrupt Mask bit (MSKI2C) in the INT_MASK
Configuration Register is unmasked (set to 1, see Interrupts Chapter).
10-bit Address Sent Event (Master Mode)
End of Byte Transfer Event
Address Matched Event (Slave Mode)
Start Bit Generation Event (Master Mode)
Acknowledge Failure Event
Stop Detection Event (Slave Mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
*
EVF can also be set by EV6 or an error from the I2C_SR2 register.
STOPF
ADD10
ARLO
BERR
ADSL
BTF
*
SB
2
AF
C interrupt events are connected to the same interrupt vector. They generate an interrupt if
Interrupt Event
ITE
ADSEL
STOPF
ADD10
BERR
Event
ARLO
Flag
BTF
SB
AF
Control
Enable
ITE
Bit
ST52F510/F513/F514
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
from
Halt
Exit
No
No
No
No
No
No
No
No
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