mcf52258 Freescale Semiconductor, Inc, mcf52258 Datasheet

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... Data Sheet: Technical Data MCF52259 ColdFire Microcontroller The MCF52259 microcontroller family (MCF52252, MCF52254, MCF52255, MCF52256, MCF52258, and MCF52259 devices member of the ColdFire reduced instruction set computing (RISC) microprocessors. This document provides an overview of the 32-bit MCF52259 microcontroller, focusing on its highly integrated and diverse feature set ...

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Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block Diagram ...

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Family Configurations Module Version 2 ColdFire Core with eMAC (Enhanced multiply-accumulate unit) and CAU (Cryptographic acceleration unit) System Clock Performance (Dhrystone 2.1 MIPS) Flash Static RAM (SRAM) Two Interrupt Controllers (INTC) Fast Analog-to-Digital Converter (ADC) USB On-The-Go (USB OTG) ...

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Family Configurations 1.1 Block Diagram Figure 1 shows a top-level block diagram of the device. Package options for this family are described later in this document. EzPD EzPCK EzPort EzPCS EzPQ To/From PADI To/From FEC PADI 4 ch DMA To/From ...

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MHz processor core frequency — 40 MHz or 33 MHz peripheral bus frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four ...

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Family Configurations — DMA or FIFO data stream interfaces — Low power consumption — OTG protocol logic • Fast Ethernet controller (FEC) — 10/100 BaseT/TX capability, half duplex or full duplex — On-chip transmit and receive FIFOs — Built-in dedicated ...

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Unused analog channels can be used as digital I/O • Four 32-bit timers with DMA support — 12.5 ns resolution at 80 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input ...

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Family Configurations — System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator — Low power modes supported n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation — 2 • Interrupt controller ...

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V2 Core Overview The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a ...

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Family Configurations 1.2.5 On-Chip Memories 1.2.5.1 SRAM The dual-ported SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary ...

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Mini-FlexBus A multi-function external bus interface called the Mini-FlexBus is provided on the device with basic functionality of interfacing to slave-only devices with a maximum slave bus frequency MHz in 1:2 mode and 80 MHz in ...

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Family Configurations The ADC can be configured to perform a single scan and halt, a scan when triggered programmed scan sequence repeatedly until manually stopped. The ADC can be configured for sequential or simultaneous conversion. When configured for ...

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The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit ...

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... MCF52254AF80 — • MCF52254CAF66 • MCF52255CAF80 MCF52256AG80 — • MCF52256CAG66 • MCF52256CVN66 MCF52256VN80 — MCF52258AG80 — • MCF52258CAG66 • MCF52258CVN66 MCF52258VN80 — • MCF52259CAG80 • MCF52259CVN80 14 freescale.com Table 2. Orderable Part Number Summary Speed Flash Encryption (MHz) (Kbytes) — 80 256 — 66 — ...

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Figure 2 shows the pinout configuration for the 144 LQFP. • FB_D4 1 FB_A14 2 FB_A13 3 FB_A12 4 FB_A11 5 FB_A10 6 VDD 7 VSS 8 TEST 9 RCON 10 TIN0 11 TIN1 12 RCC_EXTAL 13 RTC_XTAL 14 UCTS0 ...

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Family Configurations Figure 3 shows the pinout configuration for the 100 LQFP TEST 4 RCON 5 TIN0 6 TIN1 7 RTC_EXTAL RTC_XTAL 8 UCTS0 9 UTXD0 10 URXD0 11 URTS0 12 TIN3 13 ...

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Figure 4 shows the pinout configuration for the 144 MAPBGA VSS RSTOUT RSTIN FB_D6 B TEST FB_A14 FB_D4 FB_D5 C TIN1 FB_A12 FB_A13 FB_A15 RTC_ D TIN0 FB_A11 CLKMOD1 CLKMOD0 EXTAL RTC_ E UCTS0 FB_A10 RCON ...

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Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin. Table 3. Pin Functions by Primary and Alternate Purpose Primary SecondaryF Pin Group Function unction ADC AN[7:0] — VDDA — VSSA — ...

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Table 3. Pin Functions by Primary and Alternate Purpose (continued) Primary SecondaryF Tertiary Pin Group Function unction Function FEC FEC_TXEN — FEC_TXER — I2C_SCL0 — UTXD2 I2C_SDA0 — URXD2 Interrupts IRQ7 — IRQ5 FEC_MDC IRQ3 FEC_MDIO ...

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Table 3. Pin Functions by Primary and Alternate Purpose (continued) Primary SecondaryF Tertiary Pin Group Function unction Function 8 Reset RSTI — RSTO — Test TEST — Timer 3, GPT3 — PWM7 16-bit Timer 2, GPT2 — PWM5 16-bit Timer ...

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Table 3. Pin Functions by Primary and Alternate Purpose (continued) Primary SecondaryF Tertiary Pin Group Function unction Function UART 2 UCTS2 I2C_SCL1 USB_ VBUSCHG URTS2 I2C_SDA1 USB_ VBUSDIS URXD2 CANRX UTXD2 CANTX USB OTG USB_DM — USB_DP — USB_VDD — ...

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Table 3. Pin Functions by Primary and Alternate Purpose (continued) Primary SecondaryF Tertiary Pin Group Function unction Function Mini- FB_D2 USB_ 10 FlexBus VBUSE FB_D1 SYNCA FB_D0 SYNCB Standby VSTBY — Voltage 11 VDD VDD — VSS VSS — 1 ...

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Electrical Characteristics This section contains electrical specification tables and reference timing diagrams for the microcontroller unit, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The parameters specified in this data sheet supersede any values ...

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Electrical Characteristics 2.2 Current Consumption Table 5. Typical Active Current Consumption Specifications Characteristic PLL @ 8 MHz PLL @ 16 MHz PLL @ 64 MHz PLL @ 80 MHz RAM standby supply current • Normal operation: V > ...

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Table 7. Current Consumption in Low-Power Mode, Code From SRAM Mode 8 MHz (Typ) 4 Stop mode 3 (Stop 11) 4 Stop mode 2 (Stop 10) 4,5 Stop mode 1 (Stop 01) 5 Stop mode 0 (Stop 00) Wait / ...

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Electrical Characteristics Table 8. Thermal Characteristics (continued) 100 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package ...

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Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 17 Thermal resistance between the die and the case top ...

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Electrical Characteristics 2 Reprogramming of a flash memory array block prior to erase is not required. 2.5 ESD Protection Table 11. ESD Protection Characteristics Characteristics ESD target for Human Body Model ESD target for Machine Model HBM circuit description MM ...

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Table 12. DC Electrical Specifications (continued) Characteristic Output low voltage (all input/output and all output pins 2.0mA OL Output high voltage (high drive Output low voltage (high drive ...

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Electrical Characteristics Table 13. Oscillator and PLL Specifications (continued) (V Characteristic Frequency un-LOCK range Frequency LOCK range ,10 CLKOUT period jitter , measured at f • Peak-to-peak (clock edge to clock edge) • Long term (averaged over ...

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Table 15. Mini-FlexBus AC Timing Specifications Num Frequency of Operation MB1 Clock Period MB2 Output Valid MB3 Output Hold MB4 Input Setup MB5 Input Hold 1 Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE. 2 Specification ...

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Electrical Characteristics MB_CLK MB_A[19:X] MB_D[7:0] / MB_A[15:0] MB_R/W MB_ALE MB_CSn MB_OE 2.10 Fast Ethernet Timing Specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical ...

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RXCLK (Input) RXD[n:0] Figure 7. MII Receive Signal Timing Diagram 2.10.2 Transmit Signal Timing Specifications Num — TXCLK frequency E5 TXCLK to TXD[n:0], TXEN, TXER invalid E6 TXCLK to TXD[n:0], TXEN, TXER valid E7 TXCLK pulse width high E8 TXCLK ...

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Electrical Characteristics 2.10.4 MII Serial Management Timing Specifications Table 19. MII Serial Management Channel Signal Timing Num Characteristic E10 MDC cycle time E11 MDC pulse width E12 MDC to MDIO output valid E13 MDC to MDIO output invalid E14 MDIO ...

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CLKOUT GPIO Outputs GPIO Inputs 2.12 Reset Timing Table 21. Reset and Configuration Override Timing NUM Characteristic R1 RSTI input valid to CLKOUT High R2 CLKOUT High to RSTI Input invalid 2 R3 RSTI input valid time R4 CLKOUT High ...

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Electrical Characteristics 2 Table 22 Input Timing Specifications between I2C_SCL and I2C_SDA Num 11 Start condition hold time I2 Clock low period I3 SCL/SDA rise time (V I4 Data hold time I5 SCL/SDA fall time (V I6 Clock ...

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Figure 13 shows timing for the values in I2 SCL I1 SDA 2.14 Analog-to-Digital Converter (ADC) Parameters Table 24 lists specifications for the analog-to-digital converter. Name Characteristic V Low reference voltage REFL V High reference voltage REFH V ADC analog ...

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Electrical Characteristics Name Characteristic SNR Signal-to-noise ratio THD Total harmonic distortion SFDR Spurious free dynamic range SINAD Signal-to-noise plus distortion ENOB Effective number of bits 1 All measurements are preliminary pending full characterization, and made INL measured ...

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DMA Timers Timing Specifications Table 25 lists timer module AC timings. Table 25. Timer Module AC Timing Specifications Name T1 DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time T2 DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width ...

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Electrical Characteristics Num Characteristics J1 TCLK frequency of operation J2 TCLK cycle period J3 TCLK clock pulse width J4 TCLK rise and fall times J5 Boundary scan input data setup time to TCLK rise J6 Boundary scan input data hold ...

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TCLK V IL Data Inputs Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST Freescale Semiconductor J5 Input Data Valid Figure 17. Boundary Scan (JTAG) Timing J9 Input Data Valid ...

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Electrical Characteristics 2.19 Debug AC Timing Specifications Table 28 lists specifications for the debug AC timing parameters shown in Num D1 PST, DDATA to CLKOUT setup D2 CLKOUT to PST, DDATA hold D3 DSI-to-DSCLK setup 1 D4 DSCLK-to-DSO hold D5 ...

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... The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire. Table 29 lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. Device MCF52252 MCF52254 MCF52255 MCF52256 MCF52258 MCF52259 Freescale Semiconductor Table 28. D5 Current D4 Past Figure 21 ...

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Revision History 4 Revision History Revision 0 Initial public release. 1 Added package dimensions to package diagrams Added listing of devices for MCF52259 family Changed “Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse ...

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Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK MCF52259 ColdFire Microcontroller, Rev ...

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