mcs7720 MosChip, mcs7720 Datasheet
mcs7720
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mcs7720 Summary of contents
Page 1
... Universal Serial Bus (USB) input and two enhanced UART ports. This device contains all the necessary logic to communicate with the host computer via the USB Bus. In addition, the MCS7720 contains a 3.3V regulator, operates in Bus-Powered mode, and has a reduced frequency (6 MHz) crystal oscillator. This combination of features allows significant cost ...
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... MCS7720 USB-1.1 to Dual Serial Ports DP USB Interface DM Serial Interface Engine XTAL1 PLL & Clock XTAL2 Generator TEST TSTMODE Page 2 Block Diagram Descriptor Table FIFO FIFO UART - A UART - nRTS , nDTR nCTS , nDSR nRI , nCD nRTS , nDTR ...
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... XTAL1 3 XTAL2 4 GND 5 TSTPLL 6 TSTMODE 7 GND 3.3V 11 RESET 12 Rev. 1.1 USB-1.1 to Dual Serial Ports Pin-Out Diagram MCS7720CQ MCS7720 36 N.C. 35 nCTS nRTS A 31 3.3V GND nDSR A 26 nCD A 25 N.C. Page 3 ...
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... MCS7720 USB-1.1 to Dual Serial Ports Pin Assignments Name Pin Type XTAL1 3 I XTAL2 4 O TSTPLL 6 I TSTMODE I I/O RESET 12 I nCD nDSR nRTS nCD nDSR Page 4 Description Crystal oscillator input or external clock input (6 MHz). ...
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... Power and signal grounds. Device Supply inputs. All should be connected to the VOUT pin. The VOUT voltage is gated by RESET. Main Power Input. Connect to USB VBUS or local VDD. Note: All names with “n” prefix are active low. MCS7720 USB-1.1 to Dual Serial Ports Page 5 ...
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... Page 6 USB Interface All standard USB requests received from the host are processed on-board without the need of firmware intervention. The MCS7720 supports Bus- Powered operation only. The USB interface to the host controller includes a Control endpoint, a Bulk- In endpoint, a Bulk-Out endpoint and an Interrupt endpoint ...
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... Delta RI DSR CTS DCD Scratch Pad Register Divisor Latch bits[7:0] Divisor Latch bits[15:8] Bit[5] Bit[4] Bit[3] Data to be transmitted Bit[5] Bit[4] Bit[3] Data to be received MCS7720 Bit[2] Bit[1] Bit[0] Rx Stat THRE RxRdy Interrupt Interrupt Interrupt Mask Mask Mask Flush Flush FIFO ...
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... MCS7720 USB-1.1 to Dual Serial Ports Interrupt Enable Register: Serial channel interrupts are enabled using the Interrupt Enable Register (IER). Register: IER Description: Interrupt Enable Register Offset: 1 Permissions: Read/Write Bit[7] Bit[6] Reserved Bit Name 0 RxRdy Interrupt Mask 1 THRE Interrupt Mask 2 Rx Stat Interrupt Mask ...
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... Logic change Logic 1 = Flushes the content of the THR, in the same manner as FCR[1] does the RHR Reserved Reserved See the table below. FCR[7:6] 2’b00 2’b01 2’b10 2’b11 MCS7720 USB-1.1 to Dual Serial Ports Bit[2] Bit[1] Bit[0] Flush Flush Enable THR RHR FIFO ...
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... MCS7720 USB-1.1 to Dual Serial Ports Interrupt Status Register: The source of the highest priority interrupt pending is indicated by the contents of the Interrupt Status Register (ISR). There are five sources of interrupts, and four levels of priority (1 is the highest) as tabulated below. Level - Note: ISR[0] indicates whether any interrupt is pending ...
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... Parity Parity Enable LCR[1:0] 2’b00 2’b01 2’b10 2’b11 LCR[2] Data Length 0 5,6,7 6,7,8 LCR[5:3] 3’bxx0 3’b001 3’b011 3’b101 3’b111 MCS7720 Bit[2] Bit[1] Bit[0] Number of Data Stop Bits Length Data Length 5 bits 6 bits 7 bits 8 bits Stop Bits 1 5 1.5 2 Parity Type No parity Odd parity ...
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... MCS7720 USB-1.1 to Dual Serial Ports Modem Control Register: Register: MCR Description: Modem Control Register Offset: 4 Permissions: Read/Write Bit[7] Bit[6] Unused Flow Control Bit Name 0 DTR 1 RTS 2 Out1 3 Out2 Internal 4 Loop Back Enable CTS/RTS 5 flow control 6 Unused 7 Unused Page 12 Bit[5] Bit[4] 550 Mode ...
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... Logic 0 = Either there are no receiver data errors in the FIFO was cleared by earlier read of LSR Logic least one parity error, framing error or break indication in the FIFO. MCS7720 Bit[2] Bit[1] Bit[0] Parity Overrun ...
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... MCS7720 USB-1.1 to Dual Serial Ports Modem Status Register: This register provides the status of the modem control lines to CPU. Register: MSR Description: Modem Status Register Offset: 6 Permissions: Read Bit[7] Bit[6] DCD RI Bit Name 0 Delta CTS 1 Delta DSR Trailing Edge Delta DCD ...
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... Bit[4] Bit[3] Least significant Byte for divisor latch Bit[5] Bit[4] Bit[3] Most significant Byte for divisor latch Baud Rate 115.2K 57.6K 38.4K 19.2K 9600 2400 1200 600 300 150 50 MCS7720 Bit[2] Bit[1] Bit[0] Bit[2] Bit[1] Bit[0] DLM DLL (Hex) (Hex ...
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... MCS7720 USB-1.1 to Dual Serial Ports Master Reset Values Register BIT-7 RHR 0 THR X IER 0 FCR 0 IIR 0 LCR 0 MCR 0 LSR 0 MSR X SPR 0 Page 16 BIT-6 BIT-5 BIT-4 BIT-3 BIT ...
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... Condition Min C = 50pF 4 L 10 50pF 4 L 10 MCS7720 6 Volts -0 +0.3 CC -60° +150° C 4.5 to 5.5 Volts 0 to 5.5 Volts 0° +70° C 0° +115° C Typical Max Unit 3.3 3 Typical Max Unit - 0 ...
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... MCS7720 USB-1.1 to Dual Serial Ports c 48-Pin QFP Package Dimensions Page MILLIMETERS SYMBOL MIN TYPICAL A1 0.05 A2 1.35 b 0.17 c 0.09 e 0.50 L 0.45 HD 8.80 D 7.20 HE 8. INCHES MAX MIN TYPICAL MAX 0.15 0.002 0.006 1.45 0.053 0.057 0.27 0.007 0.011 0.20 0.004 0.008 ...
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... MosChip Semiconductor Technology, LTD to update or keep current the information contained in this document, nor for its use or for infringement of patent or other rights of third parties. MosChip Semiconductor Technology, LTD does not warrant or represent that any license, either expressed or implied, is granted to the user. Rev. 1.1 USB-1.1 to Dual Serial Ports IMPORTANT NOTICE MCS7720 Page 19 ...
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... MCS7720 USB-1.1 to Dual Serial Ports Revision 1.0 1.1 Page 20 Revision History Changes Preliminary Release Revised Data Sheet Date 7-Nov-2002 27-Mar-2006 Rev. 1.1 ...