MCS9845 MosChip Semiconductor, MCS9845 Datasheet
MCS9845
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MCS9845 Summary of contents
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... These can be used to add additional Serial or Parallel Ports. The MCS9845 is ideally suited for PC applications, such as high speed COM ports and parallel ports. The MCS9845 is available in a 128-pin QFP package fabricated using an advanced submicron CMOS process to achieve low drain power and high-speed requirements. ...
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... MCS9845 PCI Dual UART with ISA Bridge CLK P nRESET C I AD0 - AD31 nFRAME, nIRDY I nLOCK, IDSEL nTRDY, nSTOP, E nDEVSEL, nPARR,nSERR R F nC/BE0, nC/BE1, A nC/BE2, nC/BE3 C E nINTA EEPROM Interface Page 2 Block Diagram Serial Port Serial Port ISA ...
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... DEVSEL 26 nSTOP 27 nLOCK 28 29 nPERR nSERR 30 31 PAR nC/BE1 32 GND 33 AD15 34 AD14 35 AD13 36 AD12 37 AD11 38 Rev. 2.5 MCS9845 PCI Dual UART with ISA Bridge Pin-Out www.DataSheet4U.com 102 nCS4 101 nCS5 100 nCS6 99 GND GND ...
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... MCS9845 PCI Dual UART with ISA Bridge Pin Assignments Name Pin Type CLK 122 I nRESET 121 I AD31-29 126-128 I/O AD28-24 2-6 I/O AD23-16 11-18 I/O AD15-11 34-38 I/O AD10-8 40-42 I/O AD7-0 46-53 I/O nFRAME 23 I nIRDY 24 I nTRDY 25 O nSTOP 27 O nLOCK 28 I IDSEL 9 I nDEVSEL 26 O nPERR 29 O nSERR 30 O PAR ...
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... Master clock divided by 12 (1.8432 MHz) Standard UART clock for 115.2K data rate. Master clock divided by 6 (3.6864 MHz) Reserved pin. No connection. Master clock divided by 3 (7.3728 MHz) Reserved pin. No connection. UART-A clock input. ACLK should be connected to the 12XCLK output pin. www.DataSheet4U.com MCS9845 Page 5 ...
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... MCS9845 PCI Dual UART with ISA Bridge Name Pin Type BCLK 57 I TXA 105 O nRTSA 107 O nDTRA 106 O RXA 109 I nCTSA 111 I nDSRA 110 I nCDA 112 I nRIA 113 I TXB 76 O nRTSB 74 O nDTRB 75 O RXB 73 I nCTSB 71 I nDSRB 72 I Page 6 Description UART-B clock input ...
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... External Peripheral Read signal (Active-Low). External Peripheral Write signal (Active-Low). External Peripheral Reset Signal (Active-High). External Peripheral Reset Signal (Active-Low). External Peripheral Address Lines. External Peripheral Data Bus. External Peripheral Data Bus. Power and signal ground. Supply. Voltage www.DataSheet4U.com MCS9845 Page 7 ...
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... MCS9845 PCI Dual UART with ISA Bridge PCI Bus Operation: The execution of PCI Bus transactions take place in broadly fi ve stages: address phase; transaction claiming; data phase(s); fi nal data transfer; and transaction completion. Address Phase: Every PCI transaction starts with an address phase, one PCI clock period in duration ...
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... ID codes in place of the MosChip No guarantees are codes for example EEPROM is detected after a Hardware Reset, MosChip’s default values for the confi guration are provided by the chip itself. www.DataSheet4U.com MCS9845 By changing the Parallel Ports Serial Ports ...
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... Min Grant (00) Internal Address Select Confi guration The MCS9845 uses two Base Address Registers for its UARTs, and four for the ISA Bridge. These essentially act as internal “Chip Select” logic. Registers are addressed by using one of the Base Addresses plus an offset. ...
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... MCS9845CV EEPROM Contents (16-bit mode) EEPROM Hex Data Address Description of Content (Word) Location 0x00 9845 0x01 0000 0x02 9710 0x03 0000 0x04 0000 0x05 0000 0x06 0000 0x07 0000 0x08 0780 Class Code (23-8) 0x09 0000 0x0A 0001 0x0B 0000 0x0C 0000 ...
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... For example, the value 9845 would be written as 45 98. Changing the Device ID, Vendor ID, and Subsystem Vendor ID values requires corresponding changes in the device drivers to ensure proper functioning of the MCS9845CV. These fi elds can be customized to meet user requirements. The Subsystem Vendor ID value can be changed to arrive at a different product confi guration using the EEPROM as shown below ...
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... MCS9845 Bit-3 Bit-2 Bit-1 Bit-3 Bit-2 Bit-1 Bit-3 Bit-2 Bit-1 Receive Modem Transmit Receive Line Status Holding Status Interrupt Register Register Interrupt ...
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... MCS9845 PCI Dual UART with ISA Bridge UART Register Descriptions Transmitter Holding Register (THR) The transmitter section consists of a Transmitter Holding Register (THR) and a Transmitter Shift Register (TSR). The THR is actually a 16-Byte FIFO. Transmitter control is a function of the Line Control Register (LCR). The THR receives data off the internal data bus, and when the shift register is idle, moves it into the TSR ...
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... This bit is not used (always 0). Source Receive IIR Bit 5: Data Error This bit is not used (always 0). Receive Data Ready IIR Bits 7-6: Receive the 16C450 mode. Time-Out 1 = When FCR-0 is equal to 1. Transmitter Holding Register Empty Modem Status Change www.DataSheet4U.com MCS9845 Page 15 ...
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... MCS9845 PCI Dual UART with ISA Bridge FIFO Control Register (FCR) The FIFO Control Register (FCR write only register. The FCR enables and clears the FIFOs, as well as setting the receive FIFO trigger level. FCR Bit- 16C450 mode, disables the transmitter and receiver FIFO ...
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... Baud Rate Generator 2 during a read or write. Bit-7 must be reset during a read or write to any of the other UART 2 registers (Receiver Holding Register, Transmitter Holding Register, Interrupt Enable Register, etc.). www.DataSheet4U.com MCS9845 Parity Selection Bit-4 Bit-3 Parity type parity 0 ...
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... MCS9845 PCI Dual UART with ISA Bridge Modem Control Register (MCR) The Modem Control Register is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. MCR Bit- Sets the nDTR output pin to high Sets the nDTR output pin to low. ...
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... This bit is reset every time the CPU reads the contents of the Line Status Register. In FIFO mode, this error is associated with the particular Rev. 2.5 MCS9845 PCI Dual UART with ISA Bridge character in the FIFO to which it applies. This error is reported when its associated character is at the top of the FIFO ...
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... MCS9845 PCI Dual UART with ISA Bridge Modem Status Register (MSR) The Modem Status Register is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information ...
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... Out interrupt has not occurred, the time-out timer is 80 reset each time a new character is received or when 00 the microprocessor reads the receiver FIFO. 00 Character Time-Out and receiver FIFO Trigger- Level interrupts have the same priority as the current Receiver Data Available interrupt. www.DataSheet4U.com MCS9845 Page 21 ...
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... MCS9845 PCI Dual UART with ISA Bridge When the transmitter FIFO and THRE interrupt are enabled (FCR-0=1, IER-1=1), transmit interrupts occur as follows: The occurrence of the Transmitter Holding Register Empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two Bytes in the transmitter FIFO at the same time since the last time the transmitter FIFO was empty ...
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... Parallel Ports. Simple custom devices that always nCS6 have the CPU initiate reads or writes to the device may work without any additional Drivers, but any design that adds external components that generate Interrupt Requests will defi nitely require custom Drivers. www.DataSheet4U.com MCS9845 Page 23 ...
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... MCS9845 PCI Dual UART with ISA Bridge Electrical Characteristics Absolute Maximum Ratings Supply Voltage Voltage at any pin Operating Temperature Storage Temperature ESD HBM (MIL-STD 883E Method 3015-7 Class 2) ESD MM (JEDEC EIA/JESD22 A115-A) CDM (JEDEC/JESD22 C101-A) Latch-up (JESD No. 78, March 1997) Junction Temperature (Tj) ...
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... Positive-Going Threshold Voltage Vo Output Voltage (Low Output Voltage (High) H Input Pull-Up/Pull-Down Resistance Ri Rev. 2.5 PCI Dual UART with ISA Bridge = 4. +115 °C unless otherwise specifi ed. Min 0.7 * Vcc 2.0 3.5 www.DataSheet4U.com MCS9845 Typ Max Unit Condition 0 CMOS Vcc V CMOS 0.8 V TTL V TTL 1.84 V CMOS 3 ...
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... MCS9845 PCI Dual UART with ISA Bridge Mechanical Specifications – QFP 128 Page 26 www.DataSheet4U.com Rev 2.5 ...
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... MosChip Semiconductor Technology, LTD to update or keep current the information contained in this document, nor for its use or for infringement of patent or other rights of third parties. MosChip Semiconductor Technology, LTD does not warrant or represent that any license, either expressed or implied, is granted to the user. Rev. 2.5 PCI Dual UART with ISA Bridge IMPORTANT NOTICE www.DataSheet4U.com MCS9845 Page 27 ...
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... MCS9845 PCI Dual UART with ISA Bridge Revision 1.0 2.0 2.1 Switched to new Page-1 Layout 2.2 Corrected BAUD Rate Divisor Table 2.3 Removed text about 5V tolerant serial and PCI 2.4 Added EEPROM contents tables Updated Electrical Characteristics section Package dimensions in inches removed. 2.5 Mechanicals dimensions updated Page 28 Revision History ...