ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 20

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC2484
SERIAL INTERFACE TIMING MODES
The LTC2484’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the con-
verter can use the internal oscillator (F
HIGH) or an external oscillator connected to the F
Refer to Table 5 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle (see Figure 5).
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
Table 5. LTC2484 Interface Timing Modes
CONFIGURATION
External SCK, Single Cycle Conversion
External SCK, 3-Wire I/O
Internal SCK, Single Cycle Conversion
Internal SCK, 3-Wire I/O, Continuous Conversion
20
U
U
W
O
= LOW or F
U
SOURCE
External
External
Internal
Internal
SCK
O
pin.
O
=
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the
first rising edge) and the output data is shifted out of the
SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 32nd
falling edge of SCK (see Figure 6). On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. If the device has not finished
loading the last input bit SPD of SDI by the time CS is pulled
HIGH, the SDI information is discarded and the previous
configuration is kept. This is useful for systems not requir-
ing all 32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
CONVERSION
CS and SCK
Continuous
CONTROL
CYCLE
SCK
CS↓
CS and SCK
CONTROL
OUTPUT
Internal
DATA
SCK
CS↓
CONNECTION
WAVEFORMS
Figures 5, 6
Figures 8, 9
Figure 10
Figure 7
and
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