ltc3851-1 Linear Technology Corporation, ltc3851-1 Datasheet - Page 19

• Manufacturer Part Number: ltc3851-1
• Description: Synchronous Step-down Switching Regulator Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
The LTC3851-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the that
value. Foldback current limiting is disabled during soft-
start or tracking. Under short-circuit conditions with very
low duty cycles, the LTC3851-1 will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t
of the LTC3851-1 (≈90ns), the input voltage and inductor
value:
The resulting short-circuit current is:
Programming Switching Frequency
To set the switching frequency of the LTC3851-1, connect
a resistor, R
relationship between the oscillator frequency and R
is shown in Figure 7. A 0.1μF bypass capacitor should be
connected in parallel with R
I
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
ΔI
SC
L SC
(
=
1 4
)
750
700
650
600
550
500
450
400
350
300
250
/
=
FREQ
MaxV
20
R
t
ON MIN
SENSE
(
, between FREQ/PLLFLTR and GND. The
40
SENSE
)
60
•
V
L
R
IN
–
80
FREQ
2
1
FREQ
100
(kΩ)
Δ
I
L SC
.
(
120
)
140
38511 F07
160
ON(MIN)
FREQ
Phase-Locked Loop and Frequency Synchronization
The LTC3851-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (V
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen tary
current sources that charge or discharge the external fi lter
network connected to the FREQ/PLLFLTR pin. Note that the
LTC3851-1 can only be synchronized to an external clock
whose frequency is within range of the LTC3851-1’s internal
V
A simplifi ed block diagram is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
tinuously from the phase detector output, pulling down the
FREQ/PLLFLTR pin. When the external clock frequency is
less than f
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the fi lter capacitor C
OSCILLATOR
CO
EXTERNAL
.This is guaranteed to be between 250kHz and 750kHz.
Figure 8. Phase-Locked Loop Block Diagram
OSC
MODE/
PLLIN
, current is sourced continuously, pulling up
FREQUENCY
DETECTOR
DIGITAL
PHASE/
LP
holds the voltage.
OSC
, then current is sunk con-
2.7V
LTC3851-1
FREQ/PLLFLTR
R
LP
CO
VCO
) and a
38511 F08
19
C
38511f
LP