ltc3853euj Linear Technology Corporation, ltc3853euj Datasheet - Page 12

• Manufacturer Part Number: ltc3853euj
• Description: Triple Output, Multiphase Synchronous Step-down Controller
• Manufacturer: Linear Technology Corporation

LTC3853
OPERATION
voltage below 0.8V (e.g., SGND). To select pulse skipping
mode of operation, tie the MODE/PLLIN pin to INTV
select Burst Mode operation, fl oat the MODE/PLLIN pin.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
the voltage on the I
average inductor current is higher than the load current,
the error amplifi er EA will decrease the voltage on the I
pin. When the I
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When the controller
is enabled for Burst Mode operation, the inductor current
is not allowed to reverse. The reverse current comparator
(I
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current
is determined by the voltage on the I
mal operation. In this mode, the effi ciency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTV
LTC3853 operates in PWM pulse skipping mode at light
loads. At very light loads, the current comparator, I
may remain tripped for several cycles and force the external
top MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
effi ciency than forced continuous mode, but not nearly as
high as Burst Mode operation.
12
REV
) turns off the bottom external MOSFET just before the
TH
voltage drops below 0.5V, the internal
TH
pin indicates a lower value. If the
TH
pin, just as in nor-
CC
CC
CMP
, the
. To
TH
,
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency operation
increases effi ciency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage. The switching frequency
of the LTC3853’s controllers can be selected using the
FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ/PLLFLTR
pin can be used to program the controller’s operating
frequency from 250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3853
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized. A series R-C should be connected
between the FREQ/PLLFLTR pin and SGND to serve as
the PLL’s loop fi lter.
Power Good (PGOOD12 and PGOOD3 Pins)
The PGOOD12 pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD12 pin low when either V
voltage is not within ±7.5% of the 0.8V reference voltage.
The PGOOD12 pin is also pulled low when either RUN1
or RUN2 pin is below 1.2V or when the LTC3853 is in the
soft-start or tracking phase. When the V
is within the ±7.5% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source of up to 6V. The PGOOD12 pin will
fl ag power good immediately when both V
pins are within the ±7.5% window. However, there is an
internal 17μs power bad mask when either V
the ±7.5% window. PGOOD3 monitors V
pulled low when RUN3 is below 1.2V.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
FB3
FB1
FB
FB1
pin voltage
FB
and is also
or V
and V
is out of
FB2
3853f
pin
FB2