ltc4264cde-trpbf Linear Technology Corporation, ltc4264cde-trpbf Datasheet - Page 20

• Manufacturer Part Number: ltc4264cde-trpbf
• Description: High Power Pd Interface Controller With 750ma Current Limit
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LTC4264
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
the GND pin. Alternately, the SHDN pin can be driven
high with respect to V
that disable the signature and all LTC4264 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance is relatively large and the threshold volt-
age is fairly low. Because of high voltages present on the
printed circuit board, leakage currents from the GND pin
could inadvertently pull SHDN high. To ensure trouble-free
operation, use high voltage layout techniques in the vicinity
of SHDN. If unused, connect SHDN directly to V
Load Capacitor
The IEEE 802.3af specifi cation requires that the PD maintain
a minimum load capacitance of 5µF. It is permissible to
have a much larger load capacitor and the LTC4264 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. The LTC4264 maintains IEEE 802.3af com-
pliance when the load capacitor is 180µF or less. A larger
capacitor can be employed in a proprietary, close-system
high power application.
If the load capacitor is too large, there can be a prob-
lem with inadvertent power shutdown by the PSE. For
example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the size of the load capacitor
20
IN
. Examples of interface circuits
IN
.
and the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it is
necessary to evaluate the load current and capacitance to
ensure that inadvertent shutdown cannot occur.
Refer also to Thermal Protection in this data sheet for
further discussion on load capacitor selection.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. If either the DC
current is less than 10mA or the AC impedance is above
26.25kΩ, the PSE may disconnect power. The DC current
must be less than 5mA and the AC impedance must be
above 2MΩ to guarantee power will be removed. The PD
application circuits shown in this data sheet present the
required AC impedance necessary to maintain power.
LAYOUT CONSIDERATIONS FOR THE LTC4264
The LTC4264 is relatively immune to layout problems.
Excessive parasitic capacitance on the R
be avoided. Include an electrically isolated heat sink to
which the exposed pad on the bottom of the package can
be soldered. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be as
large as –57V for PoE applications, so high voltage layout
techniques should be employed. The SHDN pin should
be separated from other high voltage pins, like GND and
CLASS
pin should
4264f