mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 95

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Fig 19-4 EPINDEX switch function
EPCON (Endpoint Control Register, Endpoint-Indexed, Address=E1H, SYS/USB_reset=0000-0000, Read/Write)
Bit7: RXSTL-- Receive Endpoint Stall.
Bit6: TXSTL-- Transmit Endpoint Stall.
Bit5: RXDBM-- Receive Endpoint Dual Buffer Mode.
Bit4: TXDBM-- Transmit Endpoint Dual Buffer Mode.
Bit3: RXISO-- Receive Isochronous Type Enable.
Bit2: RXEPEN-- Receive Endpoint Enable.
Bit1: TXISO-- Transmit Isochronous Type Enable.
Bit0: TXEPEN-- Transmit Endpoint Enable.
The following table lists the maximum data packet size for each endpoint FIFO configuration:
MEGAWIN
RXSTL
Endpoint 3
Endpoint 2
7
Set this bit to stall the receive endpoint. When this bit is set, Device will response STALL packet to
upstream host in the handshake phase except when control setup transaction happen or RXSETUP=1.
Set this bit to stall the transmit endpoint.
Set this bit to enable the dual buffer transfer for OUT transaction. Default is cleared.
This bit is only valid for endpoint 3 receive mode.
Set this bit to enable the dual buffer transfer for IN transaction. Default is cleared.
This bit is only valid for endpoint 2.
Set this bit to configure the endpoint for Isochronous-Out transfer type. When disabled, the endpoint is for
Bulk/Interrupt-Out transfer type. The default value is 0.
This bit is only valid for endpoint 3 receive mode.
Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT
or SETUP token. This bit in endpoint 0 is enabled after reset.
Set this bit to configure the endpoint for Isochronous-In transfer type. When disabled, the endpoint is for
Bulk/Interrupt-In transfer type. The default value is 0.
This bit is only valid for endpoint 2.
Set this bit to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN
token. This bit in endpoint 0 is enabled after reset.
Endpoint 1
Endpoint 0
TXSTL
6
RXSTAT
RXCON
RXCNT
RXDAT
RXDBM
EPCON
5
TXSTAT
TXCON
TXCNT
TXDAT
TXDBM
4
MG84FL54B Data sheet
RXISO
3
EPINDEX
RXEPEN
CPU R/W
2
TXISO
1
TXEPEN
0
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