tsa5520 NXP Semiconductors, tsa5520 Datasheet - Page 6

• Manufacturer Part Number: tsa5520
• Description: 1.3 Ghz Universal Bus-controlled Tv Synthesizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PINNING
FUNCTIONAL DESCRIPTION
The device is controlled via the I
depending on the voltage applied to the SW input (pin 11).
A HIGH level on the SW input enables the 3-wire bus
inputs which are Chip Enable (CE), serial data input (SDA)
and serial clock input (SCL). A LOW level on the SW input
enables the I
Selection (AS) input], serial data input/output (SDA) and
serial clock input (SCL). The bus format selection is given
in Table 2.
I
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus receiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or the Control Byte (CB). The bits in the data
bytes are defined in Table 3.
1996 Oct 10
2
RF
V
V
V
BS4
BS3
BS2
BS1
CP
V
SW
LOCK
SCL
SDA
CE
XTAL
SYMBOL PIN
C-bus mode (SW = LOW); see Table 3
EE
CC1
CC2
tune
1.3 GHz universal bus-controlled
TV synthesizer
2
10
11
12
13
14
15
16
C-bus inputs which are CE [Address
1
2
3
4
5
6
7
8
9
RF signal input
ground
supply voltage (+5 V)
band switch supply voltage (+12 V)
PNP band switch buffer output 4
PNP band switch buffer output 3
PNP band switch buffer output 2
PNP band switch buffer output 1
charge-pump output
tuning voltage output
bus format selection input, I
3-wire
lock detector output
serial clock input
serial data input/output
chip enable/address selection input
crystal oscillator input
DESCRIPTION
2
C-bus or the 3-wire bus
2
C-bus or
6
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = 0) or control and band
switch data (first bit = 1) will follow. Until an I
command is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
The frequency register is loaded after the 8th clock pulse
of the second Divider Byte (DB2), the control register is
loaded after the 8th clock pulse of the Control Byte (CB)
and the band switch register is loaded after the 8th clock
pulse of the Band switch Byte (BB).
I
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage to the CE input.
The relationship between MA1 and MA0 and the input
voltage applied to the CE input is given in Table 5.
2
C-bus address selection
Fig.2 Pin configuration.
TSA5520; TSA5521
Product specification
2
C-bus STOP