mt36vddf12872g-202 Micron Semiconductor Products, mt36vddf12872g-202 Datasheet - Page 11

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mt36vddf12872g-202

Manufacturer Part Number
mt36vddf12872g-202
Description
1gb, 2gb X72, Ecc, Dr 184-pin Ddr Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
I
Table 9:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. F 11/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge;
and control inputs change only during active READ or WRITE commands
DD
CK =
RC =
RC =
CK =
IN
= V
Specifications
t
t
t
t
t
RC (MIN);
RAS (MAX);
CK (MIN); DQ and DQS inputs changing once per clock cycle; Address
CK (MIN); I
CK =
REF
for DQ and DQS
t
CK (MIN); DQ and DQS inputs changing twice per clock cycle
t
t
I
Values are shown for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
CK =
CK =
DD
t
CK =
OUT
Specifications and Conditions – 1GB
t
t
t
Notes:
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ and DQS inputs changing twice per
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
in I
OUT
DD
t
RC =
2P (CKE LOW) mode.
= 0mA; Address and control inputs
t
RC (MIN);
t
t
CK =
RC =
t
t
REFC =
REFC = 7.8125µs
t
t
CK (MIN); Address
RC (MIN);
t
CK =
11
1GB, 2GB (x72, ECC, DR) 184-Pin DDR RDIMM
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol -40B
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DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
2,502 2,322 2,322 2,232
3,132 3,132 2,952 2,682
2,160 1,800 1,620 1,620
1,440 1,080
2,520 2,160 1,800 1,800
3,672 3,222 2,772 2,772
3,582 3,222 2,772 2,772
9,360 9,180 8,460 8,460
8,532 7,452 6,372 6,372
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Electrical Specifications
-335
©2002 Micron Technology, Inc. All rights reserved.
144
216
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-262
144
900
216
144
-26A/
-265
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900
216
144
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA

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