mma1605wr2 Freescale Semiconductor, Inc, mma1605wr2 Datasheet - Page 9

• Manufacturer Part Number: mma1605wr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

100 Initialization to Bus Switch Closing
101
102 Communication Data Rate
103
104
105
106
107
108
109
110
111
112
113 DSI Data Latency
114
115
116
117
118
119
120
121
122
#
90
91
92
93
94
95
96
97
98
99
2.7
Sensors
Freescale Semiconductor
Reset Recovery (See
HCAP Undervoltage Reset Delay (See
V
V
V
V
V
V
BUSOUT Discharge Resistance
Loss of Signal Reset Time
BUSIN Response Current Slew Rate
BUSIN Timing to Response Current
DSI BUSIN Signal Duty Cycle
Inter-frame Separation Time (See
Bus Switch Open Time
OTP Program Timing
Self Test Response Time
Error Detection Response Time
V
HCAP
REG
REG
REGA
REGA
REG
L
POR negated to 1st DSI Command (Initialization Command)
POR negated to Acceleration Data Valid (Including LPF Init)
DSI Clear Command to 1st DSI Command (Initialization Command)
DSI Clear Command to Acceleration Data Valid (Including LPF Init)
POR to first Capacitor Test Disconnect
Disconnect Time ()
Disconnect Rate ()
Activation Time
Maximum time below frame threshold
1.0 mA to 9.0 mA, 9.0 to 1.0 mA
BUSIN Negative Voltage Transition =3.0V to I
BUSIN Negative Voltage Transition =3.0V to I
Logic ‘0’
Logic ‘1’
Following Read Write NVM Command
Following Initialization, BS = 1
Following Initialization, BS = 0
Following other DSI bus commands
Reset Asserted to I
Time to program one OTP bit
Self Test Activation time (EOF
Self Test Deactivation time (EOF
Self Test Activation time (EOF
Self Test Deactivation time (EOF
Self Test Activation time (EOF
Self Test Deactivation time (EOF
Mirror Register CRC Error to Status Flag (S) set (Factory or User Array)
≤ (V
, V
Undervoltage Reset Delay (See
< V
< V
Undervoltage Reset Delay (See
< V
REGA
Dynamic Electrical Characteristics - DSI
PORVREG_f
CC
PORHCAP_f
PORVREGA_f
Capacitor Monitor
- V
SS
to POR assertion
) ≤ V
to POR assertion
Figure
to POR assertion
SW_LEAK
H
, T
20)
Characteristic
L
≤ 20μA
Figure
≤ T
Slave
Slave
Slave
Slave
Slave
Slave
Figure
A
Figure
Figure
to 90% ΔDFLCT_xxx, 180Hz LPF)
to 90% ΔDFLCT_xxx, 400Hz LPF)
to 90% ΔDFLCT_xxx, 800Hz LPF)
≤ T
8)
to 10% ΔDFLCT_xxx, 180Hz LPF)
to 10% ΔDFLCT_xxx, 400Hz LPF)
to 10% ΔDFLCT_xxx, 800Hz LPF)
H
6)
5)
7)
, ΔT ≤ 25 K/min, unless otherwise specified
RSP
RSP
= 7.0mA rise
= 5.0mA fall
*
*
t
BUSOUT_Discharge
t
t
t
t
t
t
CAPTEST_RATE
CAPTEST_TIME
ST_DEACT_180
ST_DEACT_400
ST_DEACT_800
POR_CAPTEST
t
t
t
t
t
t
VREGA_POR
ST_ACT_180
ST_ACT_400
ST_ACT_800
t
Symbol
HCAP_POR
VREG_POR
t
t
PROG_BIT
t
t
t
t
t
DSP_INIT
DSP_INIT
BSOPEN
DSI_INIT
DSI_INIT
D
t
t
LAT_DSI
CRC_Err
RSP_R
RSP_F
D
D
t
t
t
t
t
t
RATE
t
ITR
IFS
IFS
IFS
IFS
BS
TO
CH
CL
4 / f
Min
2.00
0.33
2.00
2.00
1.00
1.00
0.50
0.50
100
200
9.5
89
10
60
20
20
64
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
OSC
12000 / f
400 / f
400 / f
880 / f
256 / f
75 / f
6 / f
Typ
10
33
67
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
OSC
OSC
OSC
OSC
OSC
OSC
OSC
10000 / f
10000 / f
5 / f
Max
10.5
4.00
10.0
2.50
2.50
5.00
5.00
2.50
2.50
1.75
1.75
138
200
500
256
40
90
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
5
OSC
OSC
OSC
MMA16xxWR
Units
mA/μs
kbps
ms
ms
ms
ms
ms
ms
ms
ms
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
%
%
s
s
s
s
s
s
s
s
s
s
9
(7)
(7)
(7)
(7)
(7)
(3)
(3)
(7)
(7)
(7)
(7)
(3)
(7)
(7)
(3)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(3)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)