mma1605nwr2 Freescale Semiconductor, Inc, mma1605nwr2 Datasheet - Page 40

• Manufacturer Part Number: mma1605nwr2
• Description: Dsi Inertial Sensor
• Manufacturer: Freescale Semiconductor, Inc

40
4.2.1.13
with the DSI Global Address of ‘0000’, but does not provide a response.
output value returning to the 0g offset value within t
Table 50. Disable Self-Test Command Bit Definitions
Table 53. Disable Self Test Response Bit Definitions
is activated, the internal self-test circuitry is disabled until one of the following conditions occurs:
MMA16xxNW
Table 49. Disable Self-Test Command
Table 52. Long Response - Disable Self-Test Command
D[15]
D[7]
A[3]
The Disable Self Test command is supported in the following command formats:
The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self Test command
The Disable Self Test Command removes the voltage from the self test plate of the transducer which results in the acceleration
A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout
⎯
Table 51. Short Response - Disable Self-Test Command
Bit Field
Bit Field
D[14]
AT[1:0]
C[3:0]
A[3:0]
D[7:0]
A[3:0]
0
NV
ST
S
U
D[14]
D[6]
A[2]
⎯
D[13]
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference
• Enhanced Short Command as configured by the Format Control Command (Reference
• HCAP undervoltage
• A Clear command is received
• Internal regulator undervoltage resulting in a reset.
• A Frame Timeout resulting in a reset.
0
Disable Self-Test Command
D[13]
D[5]
A[1]
⎯
Disable Self-Test Command = ‘1100’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference
Attribute bits located in Register DEVCFG1 (Reference
This bit indicates whether internal self-test circuitry is active
1 - Self-test active
0 - Self-test disabled
This bit is set if the voltage at HCAP is below the threshold specified in
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
DSI device address. This field contains the device address.
D[12]
0
D[12]
D[4]
A[0]
⎯
D[11]
Data
Table 59
0
D[11]
D[3]
⎯
0
D[10]
for conditions that set the S bit.
0
D[10]
D[2]
⎯
0
D[9]
0
D[1]
D[9]
⎯
0
D[8]
0
ST_DEACT_xxx
D[0]
D[8]
Response
⎯
0
Data
D[7]
NV
A[3]
D[7]
A[3]
NV
Section
D[6]
, as specified in
U
A[2]
D[6]
A[2]
Definition
Definition
U
3.1.4.2)
Address
D[5]
ST
Section
A[1]
D[5]
A[1]
ST
D[4]
0
Section
2. Refer to
A[0]
D[4]
A[0]
0
AT[1]
D[3]
2.
AT[1]
C[3]
D[3]
Section 3.3.2
1
AT[0]
D[2]
AT[0]
C[2]
D[2]
Command
1
D[1]
for details.
Freescale Semiconductor
S
Section
Section
C[1]
D[1]
S
0
D[0]
0
4.2.1.11)
C[0]
D[0]
4.2.1.11)
0
0
0 to 8 bits
CRC
0 to 8 bits
0 to 8 bits
Sensors
CRC
CRC