s908qy2ad1vdwer Freescale Semiconductor, Inc, s908qy2ad1vdwer Datasheet - Page 148
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s908qy2ad1vdwer
Manufacturer Part Number
s908qy2ad1vdwer
Description
Mc68hc908qt4a Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.S908QY2AD1VDWER.pdf
(200 pages)
- Current page: 148 of 200
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15.3.1.1 Normal Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as V
applied to the IRQ pin. If the IRQ pin is lowered (no longer V
monitor mode, but the pin functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register
BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.
If monitor mode was entered with V
IRQ.
15.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions,
(PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
148
Function
[Pin No.]
MON08
Monitor
Monitor
Normal
Forced
Mode
1. PTA0 must have a pullup resistor to V
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. Lowering V
5. X = don’t care
6. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
User
frequency / 256 and baud rate using internal oscillator is bus frequency / 335.
(PTA2)
V
V
IRQ
V
V
[6]
TST
TST
X
DD
SS
TST
once monitor mode is entered allows the clock source to be controlled by the OSCSC register.
(PTA3)
RST
RST
V
[4]
X
X
X
DD
Table 15-1. Monitor Mode Signal Requirements and Options
Vector
$FFFF
(blank)
$FFFF
(blank)
$FFFF
Reset
Not
—
X
MC68HC908QYA/QTA Family Data Sheet, Rev. 2
Communi-
cation
Serial
PTA0
COM
(CONFIG)) when V
[8]
DD
1
1
1
X
TST
OSC1
V
in monitor mode.
NC
NC
NC
NC
NC
NC
DD
on IRQ, then the COP is disabled as long as V
MOD0
PTA1 PTA4
[12]
Selection
11
13
15
X
X
X
1
1
3
5
7
9
Mode
MOD1
[10]
10
12
14
16
X
X
X
0
2
4
6
8
TST
Disabled
Disabled
Disabled
GND
RST
IRQ
PTA0
PTA4
PTA1
NC
NC
Enabled
COP
—
was lowered. With V
TST
External
) then the chip will still be operating in
9.8304
9.8304
Clock
OSC1
MHz
MHz
[13]
X
X
Communication
Frequency
(Trimmed)
Speed
3.2 MHz
2.4576
2.4576
MHz
MHz
Bus
—
X
TST
lowered, the BIH and
Freescale Semiconductor
Baud
Rate
9600
9600
9600
—
X
TST
Provide external
clock at OSC1.
Provide external
clock at OSC1.
Internal clock is
active.
is applied to
Comments
TST
is
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