mt48lc2m32b2 Micron Semiconductor Products, mt48lc2m32b2 Datasheet - Page 21

• Manufacturer Part Number: mt48lc2m32b2
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

Figure 8:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
READ Command
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x equals CL - 1. This is shown in Figure 10 on page 23 for CL = 1,
CL = 2, and CL = 3; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architecture. A READ command can be
initiated on any clock cycle following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as shown in Figure 11 on page 24, or
each subsequent READ may be performed to a different bank.
A8, A9
A0–A7
BA0, 1
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
HIGH
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
ADDRESS
COLUMN
BANK
21
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©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands