mt48lc2m32b2 Micron Semiconductor Products, mt48lc2m32b2 Datasheet - Page 26

• Manufacturer Part Number: mt48lc2m32b2
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

Figure 13:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
READ-to-WRITE With Extra Clock Cycle
Note:
COMMAND
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x equals CL - 1. This is shown in Figure 14 on
page 27 for each possible CAS latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x equals CL - 1. This is shown in Figure 15 on page 28 for each possible CAS
latency; data element n + 3 is the last desired data element of a longer burst.
ADDRESS
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
DQM
CLK
DQ
BANK,
COL n
T0
READ
T1
NOP
26
T2
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
t HZ
D
OUT
n
T4
NOP
DON’T CARE
T5
BANK,
COL b
WRITE
t
RP is met. Note that part of
D
IN
b
t
DS
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands