mt48h4m16lf Micron Semiconductor Products, mt48h4m16lf Datasheet - Page 8

• Manufacturer Part Number: mt48h4m16lf
• Description: 64mb 4 Meg X 16 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Functional Description
Initialization
Mode Register Definition
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
The 64Mb SDRAM (1 Meg x 16 x 4 banks) is a quad-bank DRAM that operates at 1.8V and
includes a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by
256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank; A0–A11 select the row). The address bits (A0–A7) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. Power should be
applied to V
and the clock is stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to
issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point
during this 100µs period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all-banks-idle state.
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
Two mode registers exist in mobile SDRAM: the mode register and the extended mode
register. The mode register is illustrated in Figure 4 on page 9, and the extended mode
register is illustrated in Figure 6 on page 12.
The mode register defines the specific mode of operation of the SDRAM, including burst
length, burst type, CAS latency, operating mode, and write burst mode. The mode
register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use and should be set to zero. M12 and M13 are set to zero to select the mode register.
DD
and V
DD
Q simultaneously. After the power is applied to V
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
Functional Description
©2006 Micron Technology, Inc. All rights reserved.
DD
and V
DD
Q