mt45w4mw16p Micron Semiconductor Products, mt45w4mw16p Datasheet
mt45w4mw16p
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mt45w4mw16p Summary of contents
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... CC F A15 DQ14 DQ13 A14 DQ5 DQ6 G A13 DQ15 A19 A12 WE# DQ7 H A18 A8 A9 A10 A11 A20 Top View (Ball Down) Designator Group 1.0 specification of -25°C. Part Number Example: MT45W4MW16PFA-70LWT ©2003 Micron Technology, Inc. All rights reserved. Features ...
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Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Ball Assignment – 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: VFBGA Ball Descriptions ...
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... General Description Micron for low-power, portable applications. The MT45W4MW16PFA is a 64Mb DRAM core device organized as 4 Meg x 16 bits. This device includes the industry-standard, asyn- chronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. Operating voltages have been reduced in an effort to minimize power consumption. The core voltage has been reduced ...
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Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol Type E3, H6, G2, H1, A[21:0] Input D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 ZZ# Input B5 CE# Input ...
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Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM Memory Operating Core Voltage W ...
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... Functional Description In general, the MT45W4MW16PFA device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W4MW16PFA contains a 67,108,864-bit DRAM core organized as 4,194,304 addresses by 16 bits. This device implements the industry-standard, asynchronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchro- nous read protocol ...
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Figure 5: READ Operation CE# OE# WE# ADDRESS DATA LB#/UB# Figure 6: WRITE Operation CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f AsyncCellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory ADDRESS VALID ...
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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is per- formed, then adjacent addresses can be quickly read by simply changing the low-order address. ...
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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to per- form the DRAM refresh operation on the full array. STANDBY operation occurs when CE# and ZZ# are HIGH. The device will ...
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Figure 8: Software Access PAR Functionality NO Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become ...
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Configuration Register Operation The configuration register (CR) defines how the CellularRAM device performs its trans- parent self refresh. Altering the refresh parameters can dramatically reduce current con- sumption during standby mode. Page mode control is also embedded into the CR. ...
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Figure 10: Software Access Load Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Note: The WRITE on the third cycle must be CE#-controlled. Figure 11: Software Access Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Notes: 1. The WRITE ...
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Figure 12: Configuration Register Bit Mapping A[21:8] 21– 8 RESERVED All must be set to "0" CR[7] Page Mode Enable/Disable 0 Page Mode Disabled (default) 1 Page Mode Enabled CR[6] CR[5] Maximum Case Temp +85˚C (default ...
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DPD operation disables all refresh-related activity. This mode will be used when the sys- tem does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been ...
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Electrical Characteristics Table 4: Absolute Maximum Ratings Parameter Voltage to Any Ball Except Voltage on V Supply Relative Voltage Supply Relative Storage Temperature Operating Temperature (case) ...
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Table 5: Electrical Characteristics and Operating Conditions Wireless Temperature Description Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage I Output Low Voltage V Input Leakage Current IN Output Leakage Current Chip Disabled Operating Current ...
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... Maximum and Typical Standby Currents The following tables and figures refer to the maximum and typical standby currents for the MT45W4MW16PFA device. The typical values shown in Figure 13 are measured with the appropriate PAR and TCR settings. The maximum values shown in Table 6 and Table 7 are measured with the relevant TCR bits set in the configuration register ...
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Figure 13: Typical Refresh Current vs. Temperature ( -30 -20 -10 0 Note: Typical I Table 8: Deep Power-Down Specifications and Conditions Description Deep Power-Down PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f AsyncCellularRAM_2.fm - Rev. G ...
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Table 9: Capacitance Specifications and Conditions Description Input Capacitance Input/Output Capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. Figure 14: AC Input/Output Reference Waveform Input V Q ...
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Table 11: READ Cycle Timing Requirements Parameter Address Access Time Page Access Time LB#/UB# Access Time LB#/UB# Disable to High-Z Output LB#/UB# Enable to Low-Z Output Maximum CE# Pulse Width Chip Select Access Time Chip Disable to High-Z Output Chip ...
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Table 12: WRITE Cycle Timing Requirements Parameter Address Setup Time Address Valid to End of Write Byte Select to End of Write CE# HIGH Time During Write Chip Enable to End of Write Data Hold from Write Time Data Write ...
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Table 13: Load Configuration Register Timing Requirements Description Address Setup Time Address Valid to End of Write Chip Deselect to ZZ# LOW Chip Enable to End of Write Write Cycle Time Write Pulse Width Write Recovery Time ZZ# LOW to ...
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Timing Diagrams Figure 16: Power-Up Initialization Period Vcc, VccQ = 1.7V Table 15: Power-Up Initialization Timing Requirements Parameter Power-Up Initialization Period Figure 17: Load Configuration Register ADDRESS CE# LB#/UB# WE# OE# ZZ# Table 16: Load Configuration Register Timing Requirements -70 ...
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Figure 18: Deep Power-Down – Entry/Exit t CDZZ t ZZ (MIN) ZZ# CE# Table 17: Deep Power-Down Timing Parameters Symbol t CDZZ (MIN) PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f AsyncCellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x ...
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Figure 19: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Table 18: READ Timing Parameters -70 Symbol Min Max BHZ t BLZ PDF: 09005aef80be1ee8/Source: ...
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Figure 20: Page Mode READ Operation (WE ADDRESS A[21:4] ADDRESS A[3:0] CE# LB#/UB# OE# DATA-OUT Table 19: Page Mode READ Timing Parameters -70 Symbol Min Max Min APA BHZ ...
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Figure 21: WRITE Cycle (WE#-Controlled) ADDRESS LB#/UB# DATA-IN DATA-OUT Table 20: WRITE Timing Parameters -70 Symbol Min Max Min PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f ...
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Figure 22: WRITE Cycle (CE#-Controlled) ADDRESS LB#/UB# DATA-IN DATA-OUT Table 21: WRITE Timing Parameters -70 Symbol Min Max Min CPH PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f ...
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Figure 23: WRITE Cycle (LB#/UB#-Controlled) ADDRESS CE# LB#/UB# WE# OE# DATA-IN DATA-OUT Table 22: WRITE Timing Parameters -70 Symbol Min Max Min PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f ...
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Figure 24: 48-Ball VFBGA 0.70 ±0.05 SEATING PLANE C 0.10 C 48X Ø0.37 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø0.35. BALL A6 5.25 2.625 ±0.05 1.875 Notes: 1. All dimensions in millimeters, MAX/MIN, or ...
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Revision History • Rev ...
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Added standard and low-power data in tables 8 & 9. • V, IT, and -60 now “contact factory. • Rev. A, Preliminary . . . . . . . . . . . . . . . . . ...