pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 72

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
11.2
11.3
12
SECONDARY CLOCK OUTPUTS
The bridge has 10 secondary clock outputs, S_CLKOUT[9:0], that can be used as clock inputs for
up to nine external secondary bus devices. In synchronous mode (ASYNC_SEL# = 1), the
S_CLKOUT[9:0] outputs are derived from P_CLK. The secondary clock edges are delayed from
P_CLK edges by a minimum of 0ns. In asynchronous mode (ASYNC_SEL# = 0), the
S_CLKOUT[9:0] outputs are derived from ASYNC_CLKIN. These are the rules for using
secondary clocks:
ASYNCHRONOUS MODE
To set the PI7C8154B into asynchronous mode, ASYNC_SEL# must be set to 0. In asynchronous
mode, the S_CLKOUT[9:0] outputs will be derived from ASYNC_CLKIN. Clock division is still
functional based on the setting of the P_M66EN and S_M66EN pins. For example, when
P_M66EN is HIGH and S_M66EN is LOW, the S_CLKOUT[9:0] outputs will be equal to half of
the ASYN_CLKIN. The PI7C8154B in asynchronous mode may run in the following frequencies:
Table 11-1 VALID ASYNCHRONOUS CLOCK FREQUENCIES
PCI POWER MANAGEMENT
PI7C8154B incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.0. These features include:
Table 12-1 shows the states and related actions that the bridge performs during power management
transitions. (No other transactions are permitted.)
Table 12-1 POWER MANAGEMENT TRANSITIONS
D0
D0
D0
Current Status
Each secondary clock output is limited to no more than one load
One of the secondary clock outputs must be used to feedback to S_CLKIN
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
Support for D0, D1, D2, D3
bridge
Support of the B2 secondary bus power state when in the D3
25MHz to 66MHz
Primary (MHz)
D3
D3
D2
COLD
HOT
Next State
HOT
and D3
HOT
COLD
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, and D3
Power has been removed from PI7C8154B. A power-up reset must be
performed to bring PI7C8154B to D0.
If enabled to do so by the BPCCE pin, PI7C8154B will disable the
secondary clocks and drive them LOW.
Unimplemented. PI7C8154B will ignore the write to the power state bits.
Power state will remain at D0.
power management states
COLD
power management states for devices behind the
*Up to 80MHz on the PI7C8154B-80 only
HOT
Action
25MHz to 66MHz*
Secondary (MHz)
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
power management state
PCI-to-PCI BRIDGE
PI7C8154B