pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 74

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
When S_RESET# is asserted, all secondary PCI interface control signals, including the secondary
grant outputs, are immediately tri-stated. Signals S_AD[31:0], S_CBE[3:0], S_PAR are driven low
for the duration of S_RESET# assertion. S_REQ64# is asserted LOW to indicate 64-bit extension
support on the secondary. All posted write and delayed transaction data buffers are reset.
Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
When S_RESET# is asserted by means of the secondary reset bit, PI7C8154B remains accessible
during secondary interface reset and continues to respond to accesses to its configuration space
from the primary interface.
13.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8154B and the
secondary bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are tri-stated.
S_RESET# is asserted and the secondary reset bit is automatically set. S_RESET# remains
asserted until a configuration write operation clears the secondary reset bit. Within 20 PCI clock
cycles after completion of the configuration write operation, PI7C8154B’s reset bit automatically
clears and PI7C8154B is ready for configuration.
During reset, PI7C8154B is inaccessible.
Page 74 of 111
MARCH 2006 REVISION 1.12
06-0008