ics87946-01 ETC-unknow, ics87946-01 Datasheet

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ics87946-01

Manufacturer Part Number
ics87946-01
Description
Lvpecl-to-lvcmos/lvttl Clock Generator
Manufacturer
ETC-unknow
Datasheet
B
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87946AY-01
G
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 10 to 20 by utilizing the ability of the outputs to
drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and part-
to-part skew characteristics make the ICS87946-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
HiPerClockS™
,&6
LOCK
ENERAL
DIV_SELC
DIV_SELA
DIV_SELB
MR/nOE
nPCLK
PCLK
D
The ICS87946-01 is a low skew, ÷1, ÷2 Clock
Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS87946-01 has one LVPECL clock
input pair. The PCLK, nPCLK pair can accept
IAGRAM
D
ESCRIPTION
÷1
÷2
0
1
0
1
0
1
www.icst.com/products/hiperclocks.html
QA0 - QA2
QB0 - QB2
QC0 - QC3
PRELIMINARY
LVPECL-
1
P
F
• 10 single ended LVCMOS outputs, 7Ω typical output
• LVPECL clock input pair
• PCLK, nPCLK supports the following input levels:
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
impedance
LVPECL, CML, SSTL
IN
EATURES
TO
DIV_SELC
DIV_SELA
DIV_SELB
A
-LVCMOS/LVTTL C
nPCLK
PCLK
SSIGNMENT
GND
V
nc
DD
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
7mm x 7mm x 1.4mm
9 10 11 12 13 14 15 16
32-Lead LQFP
ICS87946-01
Y Package
Top View
ICS87946-01
L
OW
LOCK
S
REV. A JANUARY 2, 2002
KEW
24
23
22
21
20
19
18
17
G
ENERATOR
GND
QB0
V
QB1
GND
QB2
V
V
÷1, ÷2
DDB
DDB
DDC

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ics87946-01 Summary of contents

Page 1

... G D ENERAL ESCRIPTION The ICS87946- low skew, ÷1, ÷2 Clock ,&6 Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from HiPerClockS™ ICS. The ICS87946-01 has one LVPECL clock input pair. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω ...

Page 2

... www.icst.com/products/hiperclocks.html 2 ICS87946- KEW G LOCK ENERATOR ...

Page 3

... www.icst.com/products/hiperclocks.html 3 ICS87946- KEW G LOCK = 0°C 70° ...

Page 4

... www.icst.com/products/hiperclocks.html 4 ICS87946- KEW G LOCK ENERATOR ...

Page 5

... www.icst.com/products/hiperclocks.html 5 ICS87946- KEW G LOCK = 0°C 70° ...

Page 6

... www.icst.com/products/hiperclocks.html 6 ICS87946-01 ÷1, ÷ KEW G LOCK ENERATOR 70° ...

Page 7

... DD V DDx LVCMOS GND -1.25V±5% F IGURE 87946AY-01 PRELIMINARY LVPECL- -LVCMOS/LVTTL EASUREMENT 3. IGURE UTPUT OAD EST 1B - 3.3V/2. UTPUT OAD www.icst.com/products/hiperclocks.html 7 ICS87946- KEW G LOCK I NFORMATION SCOPE Qx C IRCUIT SCOPE EST IRCUIT REV. A JANUARY 2, 2002 ÷1, ÷2 ENERATOR ...

Page 8

... Cross Points IGURE IFFERENTIAL NPUT EVEL tsk( IGURE UTPUT KEW tsk(pp IGURE ART TO ART KEW www.icst.com/products/hiperclocks.html 8 ICS87946-01 ÷1, ÷ KEW G LOCK ENERATOR V CMR REV. A JANUARY 2, 2002 ...

Page 9

... ISE AND IGURE ROPAGATION Pulse Width t PERIOD t PW odc = t PERIOD odc & t IGURE P ERIOD www.icst.com/products/hiperclocks.html 9 ICS87946- KEW G LOCK 80 20 ALL IME ELAY REV. A JANUARY 2, 2002 ÷1, ÷2 ENERATOR ...

Page 10

... PRELIMINARY LVPECL- -LVCMOS/LVTTL PPLICATION NFORMATION NPUT TO CCEPT CLK_IN + V_REF - C1 R2 0.1uF INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 10 ICS87946-01 ÷1, ÷ KEW G LOCK ENERATOR E L INGLE NDED EVELS I NPUT REV. A JANUARY 2, 2002 / ...

Page 11

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS87946-01 is: 1204 87946AY-01 PRELIMINARY LVPECL- -LVCMOS/LVTTL ...

Page 12

... ° www.icst.com/products/hiperclocks.html 12 ICS87946- KEW G LOCK ENERATOR ° REV. A JANUARY 2, 2002 ...

Page 13

... www.icst.com/products/hiperclocks.html 13 ICS87946- KEW G LOCK ENERATOR ° ...

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