ics9db401 Integrated Device Technology, ics9db401 Datasheet
ics9db401
Available stocks
Related parts for ics9db401
ics9db401 Summary of contents
Page 1
... Extended frequency range in bypass mode: Revision 333.33MHz Revision 400MHz • Real-time PLL lock detect output pin • 28-pin SSOP/TSSOP package • Available in RoHS compliant packaging 4 SPREAD COMPATIBLE PLL CONTROL LOGIC 1 DATASHEET ICS9DB401C 4 STOP DIF(3:0)) LOGIC IREF ICS9DB401C REV E 03/18/08 ...
Page 2
... OE1# 8 DIF_2 9 DIF_2# 10 VDD 11 SCLK 13 SDATA 14 OE_INV = 1 Pin Number VDD GND 1 4 SRC_IN/SRC_IN Analog VDD & GND for PLL core ICS9DB401C 28 VDDA 27 GNDA 26 IREF 25 OE_INV 24 VDD 23 DIF_6 22 DIF_6# 21 OE6# 20 DIF_5 19 DIF_5# 18 VDD 17 HIGH_BW# 16 SRC_STOP 15 PD Description DIF(1,2,5,6) IREF REV E 03/18/08 ...
Page 3
... This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 3 ICS9DB401C REV E 03/18/08 ...
Page 4
... This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 4 ICS9DB401C REV E 03/18/08 ...
Page 5
... V TYP MAX UNITS NOTES 175 200 mA 160 175 200 MHz 333.33 MHz 400 MHz 3.4 MHz 1 1 1.4 MHz 1 0 1,2 33 kHz 1,3 300 us 1 ICS9DB401C REV E 03/18/08 ...
Page 6
... MIN TYP MAX 3000 660 850 -150 150 1150 -300 250 550 140 0 175 700 175 700 125 125 and =50Ω ICS9DB401C NOTES UNITS NOTES Ω 1 1 ppm 1 ...
Page 7
... L4’ L2’ L3’ Dimension or Value Unit Figure inch 1 inch 1 inch 1 33 ohm 1 ohm 1 Dimension or Value Unit Figure inch 1 inch 1 Dimension or Value Unit Figure inch 2 inch 2 PCI Ex Board Down Device REF_CLK Input L4 PCI Ex Add In Board REF_CLK Input ICS9DB401C REV E 03/18/08 ...
Page 8
... R1a L4’ L2’ R1b R2a R2b L3’ L3 Note 3.3 Volts R5a R5b Cc Cc R6a R6b 8 Figure 3. Note ICS874003i-02 input compatible Standard LVDS R4 Down Device REF_CLK Input PCIe Device REF_CLK Input ICS9DB401C REV E 03/18/08 ...
Page 9
... ICS9DB401C Four Output Differential Buffer for PCI Express General SMBus serial interface information for the ICS9DB401C How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...
Page 10
... PWD Reserved X Disable Enable 1 Disable Enable 1 Reserved X Reserved X Disable Enable 1 Disable Enable 1 Reserved PWD Reserved X Free-run Stoppable 0 Free-run Stoppable 0 Reserved X Reserved X Free-run Stoppable 0 Free-run Stoppable 0 Reserved PWD Reserved X Reserved X Reserved X Reserved X Reserved X Reserved X Reserved X Reserved X ICS9DB401C REV E 03/18/08 ...
Page 11
... Type Type Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved Type ICS9DB401C PWD PWD PWD REV E 03/18/08 ...
Page 12
... DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion. PWRDWN# DIF DIF# Four Output Differential Buffer for PCI Express TM TM IDT /ICS and DIF# tri-stated. If the PD# drive mode bit is REF Tstable <1mS Tdrive_PwrDwn# <300uS, >200mV 12 ICS9DB401C REV E 03/18/08 ...
Page 13
... ICS9DB401C Four Output Differential Buffer for PCI Express Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. SRC_STOP# The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two consecutive rising edges of DIF recognized as a valid assertion or de-assertion ...
Page 14
... PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) Four Output Differential Buffer for PCI Express TM TM IDT /ICS 1mS 1mS 14 ICS9DB401C REV E 03/18/08 ...
Page 15
... D SEE VARIATIONS E 7.40 8.20 .291 E1 5.00 5.60 .197 e 0.65 BASIC L 0.55 0.95 .022 N SEE VARIATIONS α 0° 8° D mm. N MIN MAX 28 9.90 10.50 .390 ICS9DB401C In Inches MIN MAX -- .079 -- .073 .015 .010 SEE VARIATIONS .323 .220 0.0256 BASIC .037 SEE VARIATIONS 0° 8° D (inch) MIN MAX .413 REV E 03/18/08 ...
Page 16
... BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS a 0° 8° aaa -- 0.10 D mm. N MIN MAX 28 9.60 9.80 ICS9DB401C In Inches COMMON DIMENSIONS MIN MAX -- .047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° ...
Page 17
... ICS9DB401C Four Output Differential Buffer for PCI Express Revision History Rev. Issue Date Description 0.1 4/21/2005 Changed Ordering Information from"LN" to "LF". 1. Updated LF Ordering Information to RoHS Compliant. A 8/15/2005 2. Release to web. B 9/7/2006 Updated Electrical Characteristics. C 5/22/2007 Updated Polarity Inversion Table. D 2/28/2008 Added Input Clock Specs ...