ics9db401 Integrated Device Technology, ics9db401 Datasheet - Page 13

• Manufacturer Part Number: ics9db401
• Description: Four Output Differential Buffer For Pci Express
• Manufacturer: Integrated Device Technology

The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xI
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
SRC_STOP#
SRC_STOP# - Assertion (transition from '1' to '0')
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
ICS9DB401C
Four Output Differential Buffer for PCI Express
DIF# (Free Running)
DIF (Free Running)
DIF# (Free Running)
DIF# (Stoppable)
DIF (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
DIF (Stoppable)
SRC_Stop#
PWRDWN#
SRC_Stop#
PWRDWN#
REF.
DIF# is not driven, but pulled low by the termination. When the
13
1mS
1mS