ics650-21 Integrated Device Technology, ics650-21 Datasheet
ics650-21
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ics650-21 Summary of contents
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... Description The ICS650- low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 25 MHz crystal input to produce up to eight output clocks. The device provides clocks for PCI, SCSI, Fast Ethernet, Ethernet, USB, and AC97 ...
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... Connect to VDD. Must be same value as other VDD. Decouple with pin 14. PCLK output number 3 per table above. PCLK output number 2 per table above. Processor Select pin #0. Determines frequencies on PCLKs 1-3 per table above. Processor Select pin #1. Determines frequencies on PCLKs 1-3 per table above. 2 ICS650-21 PSEL0 PCLK1 PCLK2,3 0 25.00 50 ...
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... Max of 10 seconds Select inputs, OE Select inputs, OE VDD=3.3V, IOH=-8mA VDD=3.3V, IOL=8mA IOH=-8mA No Load, note 2 No Load, note 2 Each output Except X1 All clocks 0.8 to 2.0V 2.0 to 0.8V At VDD/2 At VDD/2 is the crystal load capacitance: Crystal caps (pF ICS650-21 Minimum Typical Maximum 7 -0.5 VDD+0 260 -65 150 3.0 5.5 2 0.8 2.4 ...
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... Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com PRELIMINARY INFORMATION System Peripheral Clock Source Marking Package ICS650R-21 20 pin SSOP ICS650R-21 20 pin SSOP ICS650R-21I 20 pin SSOP ICS650R-21I 20 pin SSOP 4 ICS650-21 20 pin SSOP Inches Inches Millimeters Millimeters Symbol Min Max Min A 0.053 0.069 1.35 A1 0.004 0.010 0. ...
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