ics650-21 Integrated Device Technology, ics650-21 Datasheet - Page 3

• Manufacturer Part Number: ics650-21
• Description: System Peripheral Clock Source
• Manufacturer: Integrated Device Technology

MDS 650-21 A
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• [phone]tel • www.icst.com
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33 may be used for each clock output. The
25.000 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental
mode, parallel resonant, 30ppm or better (to meet the Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the
following equation, where C
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
Electrical Specifications
Notes:
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, VDD = 3.3 or 5V
Operating Supply Current, IDD, at 5V
Operating Supply Current, IDD, at 3.3V
Short Circuit Current, VDD = 3.3
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, UCLCK
Output Clock Duty Cycle, PCLCK, ACLCK
One Sigma Jitter, except ACLK
One Sigma Jitter, ACLK
Absolute Clock Period Jitter PCLK, UCLK, 20M
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
2. With all clocks at highest frequencies.
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
L
is the crystal load capacitance: Crystal caps (pF) = (C
PRELIMINARY INFORMATION
Conditions
Referenced to GND
Referenced to GND
Max of 10 seconds
Select inputs, OE
Select inputs, OE
VDD=3.3V, IOH=-8mA
VDD=3.3V, IOL=8mA
IOH=-8mA
No Load, note 2
No Load, note 2
Each output
Except X1
All clocks
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
At VDD/2
3
System Peripheral Clock Source
Minimum
VDD-0.4
- 500
-0.5
-65
3.0
2.4
40
45
0
2
Typical
25.000
±50
120
50
30
50
50
75
5
L
-12) x 2. So for a
Maximum
VDD+0.5
260
150
500
ICS650-21
5.5
0.8
0.4
1.5
1.5
70
60
55
7
1
Revision 010301
Units
MHz
ppm
mA
mA
mA
pF
%
%
V
V
C
C
C
V
V
V
V
V
V
ns
ns
ps
ps
ps