is61lv2568l Integrated Silicon Solution, Inc., is61lv2568l Datasheet - Page 10

• Manufacturer Part Number: is61lv2568l
• Description: 256k X 8 High-speed Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS61LV2568L
AC WAVEFORMS
WRITE CYCLE NO. 2
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
WRITE CYCLE NO. 3
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
10
ADDRESS
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
ADDRESS
D
D
OUT
WE
OUT
D
OE
WE
CE
D
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
DATA UNDEFINED
SA
(1)
(WE Controlled: OE is LOW During Write Cycle)
(WE Controlled, OE = HIGH during Write Cycle)
Integrated Silicon Solution, Inc. — www.issi.com —
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
t
HD
t
LZWE
LZWE
t
t
HA
HA
1-800-379-4774
CE_WR2.eps
CE_WR3.eps
04/28/08
Rev. D