is61lv2568l Integrated Silicon Solution, Inc., is61lv2568l Datasheet - Page 8

• Manufacturer Part Number: is61lv2568l
• Description: 256k X 8 High-speed Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS61LV2568L
8
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1.
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
WC
SCE
AW
HA
SA
PWE
PWE
SD
HD
HZWE
LZWE
1
2
(3)
(3)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Integrated Silicon Solution, Inc. — www.issi.com —
Min.
6.5
—
(1,2)
8
7
7
0
0
6
4
0
0
- 8 ns
(Over Operating Range)
Max
—
—
—
—
—
—
—
—
—
—
3
Min. Max.
10
—
8
8
0
0
7
8
5
0
0
-10 ns
—
—
—
—
—
—
—
—
—
—
4
1-800-379-4774
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
04/28/08
Rev. D