mpc9893 Integrated Device Technology, mpc9893 Datasheet - Page 9

• Manufacturer Part Number: mpc9893
• Description: 3.3v 1 12 Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

VCO frequency and the PLL feedback divider configuration. A
high internal VCO frequency and a low PLL feedback divider
result in lower I/O jitter than the jitter limits in the AC
characteristics
Table 10
then use
specific VCO frequency and divider configuration. In above
example calculation, the internal VCO frequency of 400 MHz
corresponds to a maximum I/O jitter of 30 ps (RMS).
Table 10. Internal VCO Frequency f
depend on the output configuration and on the frequency of the
internal VCO. Using the outputs of bank A and bank B at the same
frequency (FSEL3=0) results in a lower jitter than the split output
frequency configuration (FSEL3=1). The jitter also decreases with
an increasing internal VCO frequency.
represent the maximum jitter of the MPC9893.
IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
M1M, M12M, M2M, M22M,
M1H, M12H, M2H, M22H
MPC9893
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
The I/O (Phase) jitter of the MPC9893 depends on the internal
The cycle-to-cycle jitter and period jitter of the MPC9893
500
400
300
200
100
70
60
50
40
30
20
10
M1L, M12L, M8, M82
Figure 5. Max. I/O Phase Jitter versus VCO Frequency
0
240
0
240
Configuration
MPC9893
should be used to determine the actual VCO frequency,
M3, M32
M4, M42
Figure 5
Figure 6. Max. Cycle-to-Cycle Jitter versus
260
FB=4: FSEL[0:2]=100, 111
260
(Table
Parameter: PLL/Feedback Configuration
Cycle-to-Cycle Jitter versus Frequency
I/O Phase Jitter versus Frequency
280
280
to determine the maximum I/O jitter for the
FB=6: FSEL[0:2}=010
Parameter: Output Configuration
8). When calculating the part-to-part skew,
VCO frequency [MHz]
300
PSEL3=1
300
VCO frequency [MHz]
PSEL3=0
16 * f
4 * f
6 * f
8 * f
320
320
f
VCO
FB=16: FSEL[0:2]=000, 101
ref
ref
ref
ref
FB=8: FSEL[0:2]=001, 011, 110
VCO
340
340
Figure 5
PLL Feedback
360
360
Divider FB
to
16
Figure 7
4
6
8
380
380
400
400
9
Driving Transmission Lines
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user the output drivers were designed
to exhibit the lowest impedance possible. With an output
impedance of less than 20 Ω the drivers can drive either parallel
or series terminated transmission lines. For more information on
transmission lines the reader is referred to Freescale
Semiconductor application note AN1091. In most high
performance clock networks point-to-point distribution of signals
is the method of choice. In a point-to-point scheme either series
terminated or parallel terminated transmission lines can be used.
The parallel technique terminates the signal at the end of the line
with a 50 Ω resistance to V
only a single terminated line can be driven by each output of the
MPC9893 clock driver. For the series terminated case however
there is no DC current draw, thus the outputs can drive multiple
series terminated lines.
single series terminated line versus two series terminated lines in
parallel. When taken to its extreme the fanout of the MPC9893
clock driver is effectively doubled due to its capability to drive
multiple lines.
In
In
The MPC9893 clock driver was designed to drive high speed
This technique draws a fairly high level of DC current and thus
300
250
200
150
100
50
0
240
Figure 7. Max. Period Jitter versus VCO Frequency
Figure 8. Single versus Dual Transmission Lines
MPC9893
MPC9893
Output
Output
Buffer
Buffer
14Ω
14Ω
260
280
Parameter: Output Configuration
Period Jitter versus Frequency
R
R
R
VCO Frequency
Figure 8
S
S
S
300
VCO frequency [MHz]
= 36Ω
= 36Ω
= 36Ω
CC
PSEL=xxx0
÷2.
PSEL=xxx1
MPC9893
320
illustrates an output driving a
Z
Z
Z
O
O
O
340
= 50Ω
= 50Ω
= 50Ω
REV. 7 MARCH 3, 2008
360
380
OutA
OutB0
OutB1
400