mpc9894 ETC-unknow, mpc9894 Datasheet - Page 3

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
Table 1. Pin Configurations (Continued)
Control Inputs and Outputs
EX_FB_SEL
CLK_VALID[3:0]
CLK_ALARM_RST
PLL_BYPASS
MEDIA
MR
LOCK
CLK_STAT[3:0]
SEL_STAT[1:0]
BUSY
MBOOT
PRESET
INT
MSTROUT_EN
SEL_2P5V
I
SCL
SDA
ADDR[2:0]
IEEE 1149.1 and Test
TMS
TDI
TDO
TCK
TRST
PLL_TEST[2:0]
TPA
Power and Ground
GND
V
V
V
V
V
2
1. bit order = msb to lsb.
DD
DDAB
DDCD
DDIC
DDA
C Interface
Pin
(1)
Output
Output
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Type
OD
OD
OD
—
—
—
—
—
Selects between external feedback and internal feedback
Validates the clock inputs CLK0 to CLK3 (internal pullup)
Reset of all four alarm status flags and clock selection status flag
(internal pullup)
Select static test mode (internal pulldown)
Output impedance control
Device reset (internal pullup)
PLL lock indicator
Clock input status indicator
Reference clock selection indicator
IDCS switching activity indicator
Activates I
Enables Preset configuration of configuration registers on release of
MR
Indicate any status IDCS change
Master Enable for all Outputs (internal pulldown)
Device core power supply selection for VDD and VDDA
I
I
I
JTAG test mode select (10K pullup)
JTAG test data input (10K pullup)
JTAG test data output
JTAG test clock
JTAG test reset (10K pullup)
PLL_TEST pins (factory use only, MUST BE CONNECTED TO GND)
PLL Analog test pin (factory use only, LEAVE OPEN)
Negative power supply
Positive power supply for the device core, output status and control
inputs. (3.3 V or 2.5 V)
Supply voltage for output banks A and B (QA0 through QB1)
Supply voltage for output banks C and D (QC0 through QD1) and QFB
(3.3 V or 2.5 V)
Supply voltage for differential inputs clock inputs CLK0 to CLK3 and
FB_IN (3.3 V or 2.5 V)
Clean supply for analog portions of the PLL (This voltage is derived via
a RC filter from the V
2
2
2
(3.3 V or 2.5 V)
C interface control, clock
C interface control, data
C interface address lines (10K pullup)
(internal pulldown)
2
C boot sequence (internal pulldown)
DD
supply)
Function
Supply
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
N/A
DDIC
DDIC
DDIC
DDIC
DDIC
DDA
—
—
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Active State
MPC9894
high
high
high
high
high
high
high
high
high
high
high
low
low
low
low
low
—-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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