mpc9894 ETC-unknow, mpc9894 Datasheet - Page 4

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

MPC9894
4
Table 2. Function Table
Control Inputs
PLL_BYPASS
CLK_VALID[3:0]
CLK_ALARM_RST
MR
MBOOT
PRESET
EX_FB_SEL
MEDIA
SEL_2P5V
MSTROUT_EN
Control Outputs
LOCK
BUSY
INT
CLK_STAT[3:0]
SEL_STAT[1:0]
1. The combined pins of LOCK = 1 and BUSY = 0 are used to indicate a catastrophic failure. Refer to
Control
(1)
(1)
Default
0
0
1
1
0
0
0
0
0
PLL enabled. The input to output frequency
relationship is according to
frequency locked.
The associated clock input is considered to be invalid
and usable
CLK_STAT[3:0] and SEL_STAT[1:0] flags are reset:
CLK_STAT[3:0] = 0000 and SEL_STAT[1:0] = 00.
CLK_ALARM_RST is a one-shot function.
Reset of data generators and output dividers. The
MPC9894 requires reset at power-up and after any
loss of PLL lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length of the
reset pulse should be greater than two reference clock
cycles
I
Normal Operation
Selects internal feedback path
Low output impedance (QA0 to QD1 and QFB)
Selects 3.3 V for core V
All outputs disabled (synchronous with clock being low) All outputs enabled
PLL is locked
The IDCS has initiated a clock switch.
IDCS status has changed (indicates an assertion of
CLK_STAT[3:0] or deassertion of
Associated clock input not valid
Encoded value refer to
2
C read/write mode
Table 7
DD
0
Table 9
LOCK
if the PLL is
)
PLL bypassed and IDCS disabled. The VCO output is
replaced by the reference clock signal f
considered to be a test mode and clock monitoring and
clock switching are disabled during this operation.
The associated clock input is considered to be a valid
usable clock input
CLK_STAT[3:0] and SEL_STAT[1:0] flags are active
Outputs enabled (active)
I
Uses Configuration Register PRESET values on MR
Selects external feedback path
50 Ω output impedance (QA0 to QD1 and QFB)
Selects 2.5 V for core V
PLL is unlocked
No clock switch currently performed
No status change
Associated clock input valid
Encoded value refer to
2
C boot mode
PLL Out-of-Lock
Advanced Clock Drivers Devices
Table 7
DD
Freescale Semiconductor
1
Conditions.
REF
. This is