sy89218u Micrel Semiconductor, sy89218u Datasheet - Page 9

• Manufacturer Part Number: sy89218u
• Description: Precision 1 15 Lvds Fanout Buffer With 2 1 Mux And Four ?1/?2/?4 Clock Divider Output Banks
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Functional Description
Clock Select (CLK_SEL)
CLK_SEL is an asynchronous TTL/CMOS compatible
input that selects one of the two input signals. Internal
25k_ pull-up resistor defaults the input to logic HIGH if
left open. Delay between the clock selection and
multiplexer selecting the correct input signal depends
upon the divider settings. The delay varies due to the
asynchronous nature of the input. Input switching
threshold is V
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below 100mV
Maximum frequency of the SY89218U is limited by the
FSI function. Refer to Figure 2b.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output
signal. No ringing and no undetermined state will
occur at the output under these conditions.
Please note that the FSI function will not prevent duty
cycle distortion in case of a slowly deteriorating (but
still toggling) input signal. Due to the FSI function, the
propagation delay will depend upon rise and fall time
of the input signal and on its amplitude. Refer to
“Typical Operating Characteristics” for detailed
information.
January 2007
CC
/2. Refer to Figure 2a.
PK
(200mV
PP
), typically 30mV
PK
.
9
Master Reset (/MR)
/MR is a TTL/CMOS compatible input that resets the
output signals. Internal 25k_ pull-up resistor defaults
the input to logic HIGH if left open. A LOW input to
/MR asynchronously sets the true outputs LOW and
complimentary outputs HIGH. The outputs will remain
in this state until /MR is forced HIGH. Input switching
threshold is V
Enable Outputs (EN)
EN is a synchronous TTL/CMOS compatible input that
enables/disables the outputs based on the input to
this pin. Internal 25k_ pull-up resistor defaults the
input to logic HIGH if left open. A logic LOW input
causes
complementary outputs to go HIGH. It takes 2 to 6
input
enabled/disabled because the signals are going
through a series of flip-flops. Input switching threshold
is V
CC
/2. Refer to Figure 2d and 2e.
clock
the
CC
/2. Refer to Figure 2c.
cycles
true
[e-mail]
outputs
before
to
the
or [phone]
go
M9999-012407-B
outputs
LOW
SY89218U
and
are