lmx2532 National Semiconductor Corporation, lmx2532 Datasheet - Page 7

• Manufacturer Part Number: lmx2532
• Description: Pllatinum Frequency Synthesizer System With Integrated Vcos
• Manufacturer: National Semiconductor Corporation

Functional Description
GENERAL DESCRIPTION
LMX2522/32 is a highly integrated frequency synthesizer
system that generates LO signals for PCS, Cellular CDMA
and GPS systems. These devices include all of the func-
tional blocks of a PLL, RF VCO, prescaler, RF phase detec-
tor, and loop filter. The need for external components is
limited to a few passive elements for matching the output
impedance and bypass elements for power line stabilization.
In addition to the RF circuitry, the IC also includes IF fre-
quency dividers, and an IF phase detector to complete the IF
synthesis with an external VCO and loop filter. Table 4
summarizes the counter values to generate the default IF
frequencies.
Using a low spurious fractional-N synthesizer based on a
delta sigma modulator, the circuit can support 10 kHz chan-
nel spacing for PCS, Cellular CDMA and GPS systems.
The fractional-N synthesizer enables faster lock time, which
reduces power consumption and system set-up time. Addi-
tionally, the loop filter occupies a smaller area as opposed to
the integer-N architecture. This allows the loop filter to be
embedded into the circuit, minimizing the external noise
coupling and total form factor. The delta sigma architecture
delivers very low spurious, which can be a significant prob-
lem for other PLL solutions.
The circuit also supports commonly used reference frequen-
cies of 19.20 MHz and 19.68 MHz.
FREQUENCY GENERATION
RF-PLL Section
The divide ratio can be calculated using the following equa-
tion:
LMX2522 – PCS CDMA:
f
where (RF_A
LMX2532 – Cellular CDMA:
f
where (RF_A
where
f
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤
RF_A ≤ 7 for LMX2522 or 0 ≤ RF_A ≤ 5 for LMX2532)
RF_FN: Preset numerator of binary 11-bit modulus counter
(0 ≤ RF_FN
1968 for f
f
GPS-PLL SECTION
The divide ratio can be calculated using the following equa-
tion:
LMX2522 – PCS CDMA:
f
where (RF_A
LMX2532 – Cellular CDMA:
f
where (RF_A
VCO
VCO
VCO
OSC
VCO
VCO
: Output frequency of voltage controlled oscillator (VCO)
: Reference oscillator frequency
= {8 x RF_B + RF_A + (RF_FN / f
= {6 x RF_B + RF_A + (RF_FN / f
= {6 x RF_B + RF_A + (RF_FN / f
= {8 x RF_B + RF_A + (RF_FN / f
OSC
<
<
<
<
<
= 19.68 MHz)
1920 for f
RF_B)
RF_B)
RF_B)
RF_B)
OSC
= 19.20 MHz or 0 ≤ RF_FN
OSC
OSC
OSC
OSC
) x 10
) x 10
) x 10
) x 10
4
4
4
4
} x f
} x f
} x f
} x f
OSC
OSC
OSC
OSC
<
7
where
f
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤
RF_A ≤ 5 for LMX2522 or 0 ≤ RF_A ≤ 7 for LMX2532)
RF_FN: Preset numerator of binary 11-bit modulus counter
(0 ≤ RF_FN
1968 for f
f
PCS CDMA applications using the LMX2522, if the GPS
frequency is 1355.04 MHz, Table 1 provides the proper
register settings:
Cellular CDMA applications using the LMX2532, in which the
GPS frequency is 1490.04 MHz, then Table 2 provides the
proper register settings:
Cellular CDMA applications using the LMX2532, in which the
GPS frequency is 1391.82 MHz, then Table 3 provides the
proper register settings:
IF-PLL SECTION
f
where
f
(VCO)
IF_B: Preset divide ratio of the binary 9-bit programmable
counter (1 ≤ IF_B ≤ 511)
IF_A: Preset divide ratio of the binary 4-bit swallow counter
(0 ≤ IF_A ≤ 15)
f
IF_R: Preset divide ratio of the binary 9-bit programmable
reference counter (2 ≤ IF_R ≤ 511)
From the above equation, the LMX2522/32 generates the
fixed IF frequencies as summarized in Table 4.
VCO
OSC
VCO
VCO
OSC
TABLE 1. Settings for GPS (1355.04 MHz) in LMX2522
TABLE 2. Settings for GPS (1490.04 MHz) in LMX2532
TABLE 3. Settings for GPS (1391.82 MHz) in LMX2532
Reference Frequency
Reference Frequency
Reference Frequency
: Output frequency of voltage controlled oscillator (VCO)
: Reference oscillator frequency
: Output frequency of the voltage controlled oscillator
: Reference oscillator frequency
= {16 x IF_B + IF_A} x f
19.20 MHz
19.68 MHz
19.20 MHz
19.68 MHz
19.20 MHz
19.68 MHz
OSC
<
= 19.68 MHz)
1920 for f
Cellular CDMA application
Cellular CDMA application
PCS CDMA application
OSC
OSC
= 19.20 MHz or 0 ≤ RF_FN
RF_B
RF_B
RF_B
11
11
9
9
9
8
/ IF_R where (IF_A
RF_A
RF_A
RF_A
4
2
5
3
0
6
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RF_FN
RF_FN
RF_FN
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1680
1164
1404
1422
942
<
IF_B)
<