lmx2502lq1635 National Semiconductor Corporation, lmx2502lq1635 Datasheet - Page 11

• Manufacturer Part Number: lmx2502lq1635
• Description: Pllatinum? Frequency Synthesizer System With Integrated Vco
• Manufacturer: National Semiconductor Corporation

Programming Description
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The SPI_DEF bit selects between using the default IF counter values and user programmable values. The use of the default
counter values requires that only words R0 to R3 (registers R3, loaded first, to R0, loaded last) be sent after initial power up.
The RF_LD bit activates the lock detect output of the LD pin (pin 19). The lock detect mode shows the lock status of the RF PLL.
The waveform of the lock detect mode is shown in Figure 1, in the Functional Description section on LOCK DETECT.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
11-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0
(Default)
MSB
23
SPI_
DEF
Name
SPI_DEF
RF_SEL
RF_LD
RF_B [3:0]
RF_A [2:0]
RF_FN [10:0]
22
RF_
SEL
21
RF_
LD
20
0
19
RF_B
[3:0]
18
(Continued)
17
SHIFT REGISTER BIT LOCATION
16
R0 REGISTER
Data Field
15
RF_A
[2:0]
14
11
Functions
Default Register Selection
0 = OFF (Use values set in R0 to R6)
1 = ON (Use default values set in R0 to R3)
RF VCO Selection
0 = LMX2512
1 = LMX2502
RF Lock Detect
0 = Hard zero (GND)
1 = Lock detect
RF_B Counter
4-bit programmable counter
2 ≤ RF_B ≤ 15
RF_A Counter
3-bit swallow counter
0 ≤ RF_A ≤ 7 for LMX2502
0 ≤ RF_A ≤ 5 for LMX2512
RF Fractional Numerator Counter
11-bit programmable counter
0 ≤ RF_FN
0 ≤ RF_FN
13
12
11
<
<
1920 for f
1968 for f
10
9
RF_FN
OSC
OSC
[10:0]
8
7
= 19.20 MHz
= 19.68 MHz
6
5
4
3
2
1
0
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Address
Field
LSB
0
0