vsc8164 Vitesse Semiconductor Corp, vsc8164 Datasheet - Page 3

• Manufacturer Part Number: vsc8164
• Description: 2.488 Gbit/sec To 2.7gbit/sec 1 16 Sonet/sdh Demux Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

G52239-0, Rev. 3.3
5/17/00
reliminary Datasheet
SC8164
High Speed Interface
speed inputs DI and HSCLKI. The data and clock inputs are internally terminated by a center-tapped resistor
network. For differential input DC coupling, the network is terminated to the appropriate termination voltage
V
For differential input AC coupling, the network is terminated to
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology, as shown in Figure 4. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude ( V
single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage
which has better temperature and power supply noise rejection than the on-chip resistor divider. The external
reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal,
and can be connected to either side of the differential gate.
Supplies
use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -
3.3V.
Term
In most situations these inputs will have high transition density and little DC offset. However, in cases
This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to
The incoming 2.488Gb/s data (up to 2.7Gb/s for FEC applications) and input clock are received by high
(pins HSDREF, HSCLKREF) providing a 50 to
C
C
IN
AC
TYP = 100 nF
TYP = 100 nF
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Z
Z
O
O
V
Figure 4: High Speed Serial Clock and Data Inputs
Term
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
C
C
C
IN
AC
IN
Chip Boundary
50
50
V
Term
termination for both true and complement inputs.
V
Term
V
V
CC
EE
via a blocking capacitor.
= 3.3V
= 0V
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
CMI
, V
IHSDC
) . For
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