vsc8169 Vitesse Semiconductor Corp, vsc8169 Datasheet - Page 5

• Manufacturer Part Number: vsc8169
• Description: Oc-48 Fec 16 1 Sonet/sdh Mux With Clock Generator
• Manufacturer: Vitesse Semiconductor Corp

G52230-0, Rev 3.6
01/02/01
Preliminary Data Sheet
VSC8169
or the 2x of that reference, 155.52MHz (up to 168.75MHz-FEC). REF_FREQSEL is used to select the desired
reference frequency. REF_FREQSEL = “0” designates REFCLK input as 77.76MHz (up to 84.38MHz-FEC),
REF_FREQSEL = “1” designates REFCLK input as 155.52MHz (up to 168.75MHz - FEC) . For use with the
VSC9210 FEC Encoder/Decoder chipset running at 2.654208Gb/s, REF_FREQSEL = “0” should be selected
with the REFCLK input as 82.944MHz (serial rate divided by 32).
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 4ps RMS of jitter to the output. The
VSC8169 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8169 itself during such
conditions.
Low-Speed Inputs
CLK. Off-chip termination of these inputs is required. For AC-coupling, a bias voltage suitable for AC-cou-
pling needs to be provided. See Figure 7 for external biasing resistor scheme..
where this does not hold, direct DC connection is possible. All serial data inputs have the same circuit topology,
as shown in Figure 7. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the
input signal swing should be centered about this common mode reference voltage ( V
maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user pro-
vides an external reference voltage. The external reference should have a nominal value equivalent to the com-
mon mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.
The incoming low-speed data and reference clock input are received by LVPECL inputs D[15:0] and REF-
In most situations these inputs will have high transition density and little DC offset. However, in cases
The REFCLK should be of high quality since noise on the REFCLK below the loop band width of the PLL
The customer can select to provide either a 77.76MHz (up to 84.38MHz- FEC) reference (recommended),
Z
O
Z
O
Figure 7: AC Termination of Low-Speed LVPECL REFCLK, D[15:0] Inputs
V
V
V
V
C
CC
EE
C
CC
EE
IN
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
IN
R1
R2
R1
R2
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
SEMICONDUCTOR CORPORATION
Chip Boundary
Internet: www.vitesse.com
V
V
CC
EE
= 3.3V
= 0V
Split-end equivalent termination is Z
OC-48 (FEC) 16:1 SONET/SDH
R1 = 83
MUX with Clock Generator
R2 = 125 , Zo=50 , V
V
C
for AC operation
CC
CMI
R1||R2 = Z
IN
R2 + V
R1+R2
TYP = 100nF
) and not exceed the
EE
O
R1
TERM
O
= V
to V
Term
= V
TERM
CC
-2V
Page 5