nb6l295m ON Semiconductor, nb6l295m Datasheet - Page 3

• Manufacturer Part Number: nb6l295m
• Description: 2.5v / 3.3v Dual Channel Programmable Clock/data Delay With Differential Cml Outputs
• Manufacturer: ON Semiconductor

1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and
2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected
Table 1. PIN DESCRIPTION
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
-
if no signal is applied on INx/INx input then the device will be susceptible to self-oscillation.
to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.
SLOAD
Name
SCLK
VCC1
VCC1
VCC0
VCC0
SDIN
VCC
VCC
GND
GND
VT1
VT1
VT0
VT0
IN1
IN1
IN0
IN0
EN
Q1
Q1
Q0
Q0
EP
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
CML Output
CML Output
CML Output
CML Output
Ground
I/O
SLOAD
SCLK
SDIN
VCC
VCC
EN
1
2
3
4
5
6
Figure 2. Pinout: QFN-24 (Top View)
Positive Supply Voltage for the Inputs and Core Logic
Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open
Pin Default state LOW (37 kW Pulldown Resistor).
Serial Load; This pin loads the configuration latches with the contents of the shift
register. The latches will be transparent when this signal is HIGH; thus, the data must be
stable on the HIGH-to-LOW transition of S_LOAD for proper operation. Open Pin
Default state LOW (37 kW Pulldown Resistor).
Serial Data In; This pin acts as the data input to the serial configuration shift register.
Open Pin Default state LOW (37 kW Pulldown Resistor).
Serial Clock In; This pin serves to clock the serial configuration shift register. Data from
SDIN is sampled on the rising edge. Open Pin Default state LOW (37 kW Pulldown
Resistor).
Positive Supply Voltage for the Inputs and Core Logic
Internal 50 W Termination Pin for IN1.
Noninverted differential input. Note 1. Channel 1.
Inverted differential input. Note 1. Channel 1.
Internal 50 W Termination Pin for IN1
Negative Power Supply
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to V
Noninverted Differential Output. Channel 1. Typically terminated with 50 W resistor to V
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to V
Noninverted Differential Output. Channel 0. Typically terminated with 50 W resistor to V
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
Negative Power Supply
Internal 50 W Termination Pin for IN0
Noninverted differential input. Note 1. Channel 0.
Inverted differential input. Note 1. Channel 0.
Internal 50 W Termination Pin for IN0
The Exposed Pad (EP) on the QFN-24 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat-sinking conduit. The pad is electrically connected to GND and must be connected
to GND on the PC board.
VT1
VT0
24
7
IN0
IN1
23
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8
NB6L295M
NB6L295M
IN0
IN1
22
9
3
VT0
VT1
21
10
GND
20
11
GND
VCC0
19
12
VCC1
Description
18
17
16
15
14
13
Q0
Q0
VCC0
VCC1
Q1
Q1
Exposed Pad
(EP)
CC1
CC0
CC1
CC0