nb6l295m ON Semiconductor, nb6l295m Datasheet - Page 7

• Manufacturer Part Number: nb6l295m
• Description: 2.5v / 3.3v Dual Channel Programmable Clock/data Delay With Differential Cml Outputs
• Manufacturer: ON Semiconductor

Serial Data Interface Programming
The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11-bit load cycle is required to
program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially
set PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5
and 6.
Refer to Table 7, Channel and Mode Select BIT Functions. In a load cycle, the 11-Bit Shift Register least significant bit
(clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the
delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and
the device uses both channels independently. A pulse edge entering IN0/IN0 is delayed according to the values in PD0 and exits
from Q0/Q0. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1.
When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0 and flows
through PD0 and is extended through PD1 to exit at Q1 and Q1. The most significant 9-bits, D[8:0] are delay value data for
both channels. See Figure 7.
DUAL MODE OPERATIONS
(MSB)
EXTENDED MODE OPERATIONS
(MSB)
0/1
D8
0/1
D8
Table 7. CHANNEL AND MODE SELECT BIT FUNCTIONS
PSEL
MSEL
D[8:0]
The NB6L295M is programmed by loading the 11-Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs.
BIT Name
0/1
D7
0/1
D7
PD0 Programmable Delay
PD0 Programmable Delay
0/1
0/1
D6
D6
0/1
0/1
D5
D5
Figure 3. PDO Shift Register
Figure 5. PDO Shift Register
0 Loads Data to PD0
1 Loads Data to PD1
0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path
1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs,
Q0-LOW, Q0-HIGH.
Select one of 512 Delay Values
0/1
0/1
D4
D4
0/1
0/1
D3
D3
0/1
D2
0/1
D2
0/1
D1
0/1
D1
0/1
D0
0/1
D0
MSEL
MSEL
0
1
Control
Control
Bits
Bits
PSEL
PSEL
(LSB)
(LSB)
0
0
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NB6L295M
Value
Bit
Name
Name
Value
Bit
Name
Name
7
(MSB)
(MSB)
0/1
D8
0/1
D8
Function
0/1
0/1
D7
D7
PD1 Programmable Delay
PD1 Programmable Delay
0/1
0/1
D6
D6
0/1
0/1
D5
D5
Figure 4. PD1 Shift Register
Figure 6. PD1 Shift Register
0/1
0/1
D4
D4
0/1
0/1
D3
D3
0/1
D2
0/1
D2
0/1
D1
0/1
D1
0/1
D0
0/1
D0
MSEL
MSEL
0
1
Control
Control
Bits
Bits
PSEL
PSEL
(LSB)
(LSB)
1
1
Value
Bit
Name
Name
Value
Bit
Name
Name