w83194br-619 Winbond Electronics Corp America, w83194br-619 Datasheet - Page 12

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w83194br-619

Manufacturer Part Number
w83194br-619
Description
Winbond Clock Generator For Intel P4 Springdale Series Chipset P4 Springdale Series Chipset
Manufacturer
Winbond Electronics Corp America
Datasheet
7.
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1
7.2
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
I
Register 0: Frequency Select Register (Default =18H)
Register 1: SRC/CPU Clock Register (1 = Enable, 0 = Disable) (Default =E3H)
EN_SAFE_FREQ
2
C CONTROL AND STATUS REGISTERS
CPUCLKC1
CPUCLKC0
CPUCLKT1
CPUCLKT0
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
SRCCLKC
SRCCLKT
EN_SSEL
SPSPEN
SSEL [4]
SSEL [3]
SSEL [2]
SSEL [1]
SSEL [0]
NAME
NAME
FS4
FS3
FS2
FS1
FS0
PWD
PWD
X
X
X
X
X
1
1
1
0
0
0
1
1
0
0
0
Pin 37,36 SRCCLK T/C output control
Pin 43,42 CPUCLKT1/C1 output control
Pin 40,39 CPUCLKT0/C0 output control
Power on latched value of FS4 (9) pin.
Power on latched value of FS3 (22) pin.
Power on latched value of FS2 (8) pin.
Power on latched value of FS1 (1) pin.
Power on latched value of
Software frequency table selection through I
Enable software table selection FS [4:0].
0 = Hardware table setting (Jump mode).
1 = Software table setting through Bit7~3. (Jump less mode)
Enable spread spectrum mode under clock output.
0 = Spread Spectrum mode disable
1 = Spread Spectrum mode enable
After watchdog timeout
0 = Reload the hardware FS [4:0] latched pins setting.
1 = Reload the desirable frequency table selection defined at Reg-5
Bit 4~0.
W83194BR-619/W83194BG-619
- 8 -
FS0
DESCRIPTION
DESCRIPTION
(2) pin.
2
C

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