idt49c460cjb Integrated Device Technology, idt49c460cjb Datasheet - Page 7

• Manufacturer Part Number: idt49c460cjb
• Description: 32-bit Cmos Error Detection And Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
DETAILED PRODUCT DESCRIPTION
generate check bits on 32 bits of data input according to a
modified Hamming Code. The EDC can compare internally
generated check bits against those read with the 32-bit data
to allow correction of any single bit data error and detection of
all double (and some triple) bit errors. The IDT49C460s can
be used for 32-bit data words (7 check bits) and 64-bit (8 check
bits) data words.
WORD SIZE SELECTION
determine the data word size that is 32 or 64 bits. They also
select the Internal Control Mode. Table 4 defines all possible
slice identification codes.
CHECK AND SYNDROME BITS
bits on the three-state output pins, SC
generated from a combination of the Data Input bits, while
syndrome bits are an exclusive-OR of the check bits gener-
ated from read data with the read check bits stored with the
data. Syndrome bits can be decoded to determine the single
bit in error or that a double (some triple) error was detected.
The check bits are labeled:
C
C
Syndrome bits are similarly labeled S
NOTES:
1. In Generate Mode, data is read into the EDC unit and the check bits are generated. The same data is written to memory along with the check bits. Since
2. Error Dep (Error Dependent):
3. LE
Generate
Detect
Correct
PASSTHRU
Diagnostic
Generate
Diagnostic Detect
Diagnostic Correct
Initialization
Internal
0
0
, C
, C
The IDT49C460 EDC units contain the logic necessary to
The two code identification pins, CODE ID
The IDT49C460s provide either check bits or syndrome
the DATA
for no errors.
Operating
IN
1
1
, C
, C
is LOW.
Mode
2
2
, C
, C
OUT
3
3
Latch is not used in the Generate Mode, LE
, C
, C
4
4
, C
, C
CODE ID
DM
5
5
0
1
0
0
0
0
1
0
1
1
1
, C
, C
0
6
6
, C
ERROR
DM
1,0
0
0
0
1
0
1
1
1
0
0
1
7
1
= 01 (Control Signals CODE ID
for the 32-bit configuration
for the 64-bit configuration
will be low for single or multiple errors, with
Generate
0
0
1
1
1
0
1
1
1
through S
0–7
. Check bits are
1, 0
Table 3. IDT49C460 Operating Modes
Correct
, are used to
7
OUT
.
X
X
0
1
0
0
1
1
(being LOW since it is tied to Generate) does not affect the writing of check bits.
Single Bit Correction
Single Bit Correction
LE
DATA
DATA
DATA
1,0
11.6
DATA
DATA
DATA
DATA
Set to 0000
OUT
, DIAG MODE
IN
IN
OUT
Correct
= LOW
IN
IN
—
IN
IN
Latch w/
Latch w/
0/1
Latch
Latch
Latch
Latch
X
X
1
0
MULT ERROR
Latch
(3)
(1)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1,0
Mode
Diag
Check Bits from Diagnostic Latch
and CORRECT are taken from Diagnostic Latch.)
0
0
1
1
1
Table 2. Diagnostic Mode Control
low for double or multiple errors. Both signals are high
Check Bits Generated from
0
Syndrome Bits DATA
Syndrome Bits DATA
Syndrome Bits DATA
Syndrome Bits DATA
Mode
Diag
Diagnostic Latch
Diagnostic Latch
Check Bit Latch
Check Bit Latch
Check Bit Latch
0
1
0
1
1
(
DATA
OE OE
1
SC
SC
Non-diagnostic Mode.
EDC function in this mode.
Diagnostic Generate.
tents of the Diagnostic Latch are
substituted
generated check bits when in the
Generate
functions normally in the Detect or
Correct modes.
Diagnostic Detect/Correct.
either mode, the contents of the
Diagnostic Latch are substituted
for the check bits normally read
from the Check Bit Input Latch.
The EDC functions normally in the
Generate Mode.
Initialize. The Data Input Latch
outputs are forced to zeros and
latched upon removal of Initialize
Mode.
PASSTHRU.
IN
—
= LOW)
0–7
Latch
Diagnostic Mode Selected
IN
IN
IN
IN
Mode.
/
/
/
/
for
the
MULT ERROR
MULT ERROR
Error Dep
Error Dep
Error Dep
Error Dep
ERROR
ERROR
The
High
High
High
The con
—
normally
Normal
2584 tbl 02
2584 tbl 03
EDC
(2)
7
In