lmk04000bisqx National Semiconductor Corporation, lmk04000bisqx Datasheet - Page 18

• Manufacturer Part Number: lmk04000bisqx
• Description: Lmk04000 Family Of Precision Clock Conditioners Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

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Note 8: Load conditions for output clocks: LVPECL: 50 Ω to V
Note 9: Additional test conditions for I
Note 10: CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz.
Note 11: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is
0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the
device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible
to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest
possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Note 12: This parameter is programmable
Note 13: F
Note 14: The EN_PLL2_REF2x bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
Note 15: See Application Section discussion of Crystal Power Dissipation.
Note 16: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of
L
Note 17: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L
(f)-20log(N)-10log(f
frequency of the synthesizer. L
Note 18: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous
lock, then it will be necessary to reload the R0 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the
temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
Note 19: For LMK040X0, f
VCO_DIV=3, N2=5, R2=1, F
dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 20: For LMK040X1, f
VCO_DIV=3, N2=5, R2=1, F
dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 21: For LMK040x3, f
VCO_DIV=2, N2=10, R2=1, F
dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 22: For LMK040X0, f
VCO_DIV=5, N2=5, R2=1, F
Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV=2. CLKOUT_DLY=OFF.
Note 23: For LMK040X1, f
VCO_DIV=3, N2=5, R2=1, F
dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV=2. CLKOUT_DLY=OFF.
Note 24: For LMK040x3, f
VCO_DIV=2, N2=10, R2=1, F
dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV=4. CLKOUT_DLY=OFF.
Note 25: For LMK040x0, F
of PLL2. PLL2 parameters: VCO_DIV=5, N2=5, R2 = 1, F
parameters: CLKoutX_DIV=2, CLKOUT_DLY=OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
Note 26: For LMK040x1, F
of PLL2. PLL2 parameters: VCO_DIV=3, N2=5, R2 = 1, F
parameters: CLKoutX_DIV=2, CLKOUT_DLY=OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
Note 27: For LMK040x3, F
PLL2. PLL2 parameters: VCO_DIV=2, N2=10, R2=1, F
parameters: CLKoutX_DIV=4, CLKOUT_DLY=OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
Note 28: Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production.
Note 29: For LMK040x1, F
ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV=3, N2=20, R2=1, F
12 nF, R2 = 1.8 KΩ, R3 = 600 Ω, R4 = 10 KΩ, C3 = 150 pF, C4 = 60 pF, LBW = 103 kHz, PM = 44°, CLKoutX_DIV=2, CLKOUT_DLY=OFF.
Note 30: For LMK040x3, F
ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV=4, N2=20, R2=1, F
12 nF, R2 = 1.8 KΩ, R3 = 600 Ω, R4 = 10 KΩ, C3 = 150 pF, C4 = 60 pF, LBW = 91 kHz, PM = 47°, CLKoutX_DIV=2, CLKOUT_DLY=OFF.
Note 31: For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to ½ of a period, or, 0.5/F
Note 32: Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode.
Note 33: LVPECL/2VPECL is programmable for all NSIDs.
Note 34: Guaranteed by characterization.
PLL_flicker
(f) and L
OSCin
maximum frequency guaranteed by characterization. Production tested at 200 MHz.
PLL_flat
COMP
(f).
). L
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
PLL_flat
DET
DET
DET
DET
=2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCIN input of PLL2. PLL2 parameters:
=2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCIN input of PLL2. PLL2 parameters:
=1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCIN input of PLL2. PLL2 parameters:
=1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCIN input of PLL2. PLL2 parameters:
=1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCIN input of PLL2. PLL2 parameters:
=1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCIN input of PLL2. PLL2 parameters:
DET
DET
=1474.56 MHz. PLL1 parameters: F
=1966.08 MHz. PLL1 parameters: F
=1250 MHz. PLL1 parameters: F
=1500 MHz. PLL1 parameters: F
=2000 MHz. PLL1 parameters: F
PLL_flat
=50 MHz, ICP2=1.6 mA, C1=22 pF, C2=5.6 nF, R2=1.8 KΩ, LBW=163 kHz, PM=77°. Wenzel XO phase noise: 100 Hz: -132 dBc/
=100 MHz, ICP2=1.6 mA, C1=22 pF, C2=5.6 nF, R2=1.8 KΩ, LBW=268 kHz, PM=75°. Wenzel XO phase noise: 100 Hz: -132
=100 MHz, ICP2=1.6 mA, C1=22 pF, C2=5.6 nF, R2=1.8 KΩ, LBW=268 kHz, PM=75°. Wenzel XO phase noise: 100 Hz: -132
=100 MHz, ICP2=1.6 mA, C1=22 pF, C2=5.6 nF, R2=1.8 KΩ, LBW=268 kHz, PM=75°. Wenzel XO phase noise: 100 Hz: -132
=100 MHz, ICP2=1.6 mA, C1=22 pF, C2=5.6 nF, R2=1.8 KΩ, LBW=434 kHz, PM=69°. Wenzel XO phase noise: 100 Hz: -132
=100 MHz, ICP2=1.6 mA, C1=22 pF, C2=5.6 nF, R2=1.8 KΩ, LBW=434 kHz, PM=69°. Wenzel XO phase noise: 100 Hz: -132
(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and f
(f) contributes to the total noise, L(f).
CC
limits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 31 for more information)
DET
DET
DET
=100 MHz, ICP2=1.6 mA, C1 =0 pF, C2=12 nF, R2 =1.8 KΩ, LBW = 445 kHz, PM = 76°. CLKDIST
= 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 KΩ, LBW = 271 kHz, PM = 80°. CLKDIST
= 50 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 KΩ, LBW = 164 kHz, PM = 83°. CLKDIST
CC
DET
DET
DET
-2 V. 2VPECL: 50 Ω to V
DET
DET
= 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCIN input
=1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCIN input
=1 MHz, ICP1=100 µA, loop bandwidth=20 Hz. A 100 MHz VCXO drives the OSCIN input of
=1.024 MHz, ICP1=100 µA, loop bandwidth=20 Hz. A 12.288 MHz Ecliptek crystal (model:
=1.024 MHz, ICP1=100 µA, loop bandwidth=20 Hz. A 12.288 MHz Ecliptek crystal (model:
18
PLL_flicker
CC
-2.36 V. LVDS: 100 Ω differential. LVCMOS: 10 pF.
(f), which is dominant close to the carrier. Flicker noise has a 10
PLL_flicker
PLL_flicker
(10 kHz) - 20log(Fout / 1 GHz), where L
DET
DET
PLL_flat
=24.576 MHz, ICP2=3.2 mA, C1=0 pF, C2=
=24.576 MHz, ICP2=3.2 mA, C1=0 pF, C2=
(f) it is important to be on the 10 dB/decade
CLKoutX
(f), is defined as: PN1HZ=L
.
COMP
is the phase detector
PLL_flat
PLL_flicker
PLL_flicker
(f)