lmk02002 National Semiconductor Corporation, lmk02002 Datasheet - Page 12

• Manufacturer Part Number: lmk02002
• Description: Precision Clock Conditioner With Integrated Pll
• Manufacturer: National Semiconductor Corporation

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2.6 Register R15
2.6.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider.
The PLL N Divider follows the VCO Divider and precedes the
PLL phase detector. Since the VCO Divider is also in the
feedback path from the VCO to the PLL Phase Detector, the
total N divide value, N
vider value. N
frequency is calculated as, f
VCO Divider / PLL R Divider. Since the PLL N divider is a pure
binary counter, there are no illegal divide values for PLL_N
[17:0] except for 0.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
Total
PLL_N[17:0]
= PLL N Divider × VCO Divider. The VCO
Total
, is also influenced by the VCO Di-
VCO
= f
OSCin
× PLL N Divider ×
(default)
Divider
262143
PLL N
Invalid
Value
760
...
...
1
12
2.6.2 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
PLL_CP_GAIN[1:0]
0
1
2
3
Charge Pump Gain
1x (default)
16x
32x
4x