nb3n508s ON Semiconductor, nb3n508s Datasheet - Page 3

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nb3n508s

Manufacturer Part Number
nb3n508s
Description
3.3v, 216 Mhz Pureedge Vcxo Clock Generator With Mlvds Output
Manufacturer
ON Semiconductor
Datasheet

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Recommended Crystal Parameters
Crystal Fundamental AT−Cut Frequency
Load Capacitance
Shunt Capacitance, C0
Max Equivalent Series Resistance
Max Initial Accuracy at 25°C
Temperature Stability
Aging
C0/C1 Ration
Table 1. PIN DESCRIPTION
2, 3, 4, 10
6, 7, 8, 12
9, 11, 15
Pin
13
14
16
1
5
Name
GND
CLK
CLK
V
V
NC
X1
X2
DD
IN
M−LVDS Output
M−LVDS Output
Power Supply
Power Supply
Crystal Input
Crystal Input
GND
GND
GND
V
V
V
V
X1
DD
DD
DD
IN
Input
I/O
1
2
3
4
5
6
7
8
Figure 2. Pin Configuration (Top View)
27 MHz
14 pF
7 pF
35 W
±20 ppm
±30 ppm
±20 ppm
250 Max
Crystal input(IN). Connect to a 27 MHz crystal.
Positive power supply voltage.
Analog voltage input pin that controls output oscillation frequencies. V
from 0 V to 3.3 V. V
Ground 0 V. These pins provide GND return path for the devices.
No Connect.
Inverted clock output. Typically loaded with 50 W receiver termination resistor across
diff. pair.
Noninverted clock output. Typically loaded with 50 W receiver termination resistor
across diff. pair.
Crystal input(OUT). Connect to a 27 MHz crystal.
http://onsemi.com
NB3N508S
3
IN
voltage should not exceed V
Description
16
15
14
13
12
11
10
9
X2
NC
CLK
GND
NC
NC
CLK
V
DD
DD
.
IN
pin range is

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